Brandon Noia

Publication Activity (10 Years)

Years Active: 2009-2015
Publications (10 Years): 1

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

3DIC

J. Electron. Test.

VTS

Duke University, Durham, NC, USA (PHD)

Education History

Duke University, Durham, NC, USA

PHD

Publications

Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim
Scan Test of Die Logic in 3-D ICs Using TSV Probing. IEEE Trans. Very Large Scale Integr. Syst. 23 (2) (2015)
Krishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye
Test and Design-for-Testability Solutions for 3D Integrated Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 7 (2014)
Brandon Noia, Krishnendu Chakrabarty
Retiming for Delay Recovery After DfT Insertion on Interdie Paths in 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (3) (2014)
Zhenqian Zhang, Brandon Noia, Krishnendu Chakrabarty, Paul D. Franzon
Face-to-face bus design with built-in self-test in 3D ICs. 3DIC (2013)
Brandon Noia, Krishnendu Chakrabarty
Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs. VTS (2013)
Brandon Noia, Krishnendu Chakrabarty
Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (4) (2013)
Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen
Optimization Methods for Post-Bond Testing of 3D Stacked ICs. J. Electron. Test. 28 (1) (2012)
Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim
Scan test of die logic in 3D ICs using TSV probing. ITC (2012)
Brandon Noia, Krishnendu Chakrabarty
Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips. IET Comput. Digit. Tech. 5 (3) (2011)
Brandon Noia, Krishnendu Chakrabarty
Testing and Design-for-Testability Techniques for 3D Integrated Circuits. Asian Test Symposium (2011)
Brandon Noia, Krishnendu Chakrabarty
Pre-bond probing of TSVs in 3D stacked ICs. ITC (2011)
Brandon Noia, Krishnendu Chakrabarty
Identification of Defective TSVs in Pre-Bond Testing of 3D ICs. Asian Test Symposium (2011)
Brandon Noia, Krishnendu Chakrabarty
Pre-bond testing of die logic and TSVs in high performance 3D-SICs. 3DIC (2011)
Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree
Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (11) (2011)
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree
Test-architecture optimization for TSV-based 3D stacked ICs. ETS (2010)
Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen
Optimization methods for post-bond die-internal/external testing in 3D stacked ICs. ITC (2010)
Brandon Noia, Krishnendu Chakrabarty, Yuan Xie
Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs. ICCD (2009)

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Publication Activity (10 Years)

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Brandon Noia