Jürgen Koehl

Publication Activity (10 Years)

Years Active: 1991-2008
Publications (10 Years): 0

Publications

Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl
Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI (2008)
Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl
Robust wiring networks for DfY considering timing constraints. ACM Great Lakes Symposium on VLSI (2007)
Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. DATE (2006)
Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller, Sven Peyer, Christian Schulte
Yield Improvement by Local Wiring Redundancy. ISQED (2006)
Jürgen Koehl, David E. Lackey, George W. Doerre
IBM's 50 Million gate ASICs. ASP-DAC (2003)
David E. Lackey, Paul S. Zuchowski, Jürgen Koehl
Designing mega-ASICs in nanogate technologies. DAC (2003)
Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni
Automatic Hierarchical Design: Fantasy or Reality? (Panel). ICCAD (2001)
Jürgen Koehl, Jürgen Schietke
Platzierungsbasierte Logikoptimierung komplexer VLSI Chips. MBMV (2000)
Tilmann Stöhr, Markus Alt, Asmus Hetzel, Jürgen Koehl
Analysis, reduction and avoidance of crosstalk on VLSI chips. ISPD (1998)
Jürgen Koehl, Ulrich Baur, Thomas Ludwig, Bernhard Kick, Thomas Pflueger
A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset. DATE (1998)
Bernhard Kick, Ulrich Baur, Jürgen Koehl, Thomas Ludwig, Thomas Pflueger
Standard-cell-based design methodology for high-performance support chips. IBM J. Res. Dev. 41 (4&5) (1997)
Ren-Song Tsay, Jürgen Koehl
An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement. DAC (1991)