Markus Bühler

Publication Activity (10 Years)

Years Active: 1998-2017
Publications (10 Years): 4

Top Topics

Sequence Alignment

Target Detection And Tracking

Materials Science

Infrared Camera

Top Venues

Publications

Paul F. Baumeister, B. Rombach, Thorsten Hater, Sabine Griessbach, L. Hoffmann, Markus Bühler, Dirk Pleiter
Strategies for Forward Modelling of Infrared Radiative Transfer on GPUs. PARCO (2017)
Alexander Berreth, Benedetto Risio, Markus Bühler, Benedikt Anlauf, Pascal Vezolle
Performance of the 3D Combustion Simulation Code RECOM®-AIOLOS on IBM® POWER8® Architecture. ISC Workshops (2016)
Paul F. Baumeister, Marcel Bornemann, Markus Bühler, Thorsten Hater, Benjamin Krill, Dirk Pleiter, Rudolf Zeller
Addressing Materials Science Challenges Using GPU-accelerated POWER8 Nodes. Euro-Par (2016)
Thorsten Hater, Benedikt Anlauf, Paul F. Baumeister, Markus Bühler, Jiri Kraus, Dirk Pleiter
Exploring Energy Efficiency for GPU-Accelerated POWER Servers. ISC Workshops (2016)
Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez
Design methodology for the IBM POWER7 microprocessor. IBM J. Res. Dev. 55 (3) (2011)
Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz
A theoretical probabilistic simulation framework for dynamic power estimation. ICCAD (2011)
Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz
A gate sizing method for glitch power reduction. SoCC (2011)
Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler
Fast dynamic power estimation considering glitch filtering. SoCC (2009)
Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl
Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI (2008)
Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. DATE (2006)
Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller, Sven Peyer, Christian Schulte
Yield Improvement by Local Wiring Redundancy. ISQED (2006)
Markus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach. DATE (1999)
K. Kapp, Markus Bühler, D. Dallmann, Utz G. Baitinger
TESA: Timeparallel Estimation of Switching Activity under a real delay model. ICECS (1998)
Markus Bühler, D. Dallmann, Utz G. Baitinger
Switching Activity Analysis Using a Set Theoretical Approach. MBMV (1998)