Erich Barke

Publication Activity (10 Years)

Years Active: 1983-2019
Publications (10 Years): 3

Top Topics

Suboptimal Solutions

Polynomial Equations

Analog Circuits

Iterated Local Search

Top Venues

Publications

Carna Zivkovic, Christoph Grimm, Markus Olbrich, Oliver Scharf, Erich Barke
Hierarchical Verification of AMS Systems With Affine Arithmetic Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (10) (2019)
Bjorn Bredthauer, Markus Olbrich, Erich Barke
STP - A Quadratic VLSI Placement Tool Using Graphic Processing Units. ISPDC (2018)
Erich Barke, Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher
Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis. DATE (2016)
Hyun-Sek Lukas Lee, Matthias Althoff, Stefan Hoelldampf, Markus Olbrich, Erich Barke
Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits. ASP-DAC (2015)
Artur Quiring, Markus Olbrich, Erich Barke
Fast global interconnnect driven 3D floorplanning. VLSI-SoC (2015)
Oliver Scharf, Markus Olbrich, Erich Barke
Split and merge strategies for solving uncertain equations using affine arithmetic. SimuTools (2015)
Michael Kärgel, Markus Olbrich, Erich Barke
Simulation Based Verification with Range Based Signal Representations for Mixed-Signal Systems. SBCCI (2014)
C. Katzschke, M.-P. Sohn, Markus Olbrich, Volker Meyer zu Bexten, Markus Tristl, Erich Barke
Application of Mission Profiles to enable cross-domain constraint-driven design. DATE (2014)
Artur Quiring, Markus Olbrich, Erich Barke
Improving 3D-Floorplanning using smart selection operations in meta-heuristic optimization. 3DIC (2013)
Stefan Hoelldampf, Hyun-Sek Lukas Lee, Daniel Zaum, Markus Olbrich, Erich Barke
Efficient generation of analog circuit models for accelerated mixed-signal simulation. SoCC (2012)
Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz
A theoretical probabilistic simulation framework for dynamic power estimation. ICCAD (2011)
Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz
A gate sizing method for glitch power reduction. SoCC (2011)
M. Zhang, R. Haussler, Markus Olbrich, Harald Kinzelbach, Erich Barke
A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization. VLSI Design (2011)
Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke
Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation. ICCD (2011)
Artur Quiring, Marc Lindenberg, Markus Olbrich, Erich Barke
-tree. 3DIC (2011)
Florian Schupfer, Christoph Grimm, Markus Olbrich, Michael Kärgel, Erich Barke
Towards Abstract Analysis Techniques for Range Based System Simulations. FDL (2010)
Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann
An Accelerated Mixed-Signal Simulation Kernel for SystemC. FDL (2010)
Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler
Fast dynamic power estimation considering glitch filtering. SoCC (2009)
Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt
The PRAISE approach for accelerated transient analysis applied to wire models. BMAS (2009)
Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang
Formal approaches to analog circuit verification. DATE (2009)
Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt
Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). FDL (2008)
Darius Grabowski, Markus Olbrich, Erich Barke
Analog circuit simulation using range arithmetics. ASP-DAC (2008)
Markus Olbrich, Erich Barke
Distribution arithmetic for stochastical analysis. ASP-DAC (2008)
Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl
Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI (2008)
Peter Leppelt, Erich Barke
Determining the Technical Complexity of Integrated Circuits. DATE (2008)
Thomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke
A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. DDECS (2008)
Darius Grabowski, Markus Olbrich, Christoph Grimm, Erich Barke
Range Arithmetics to Speed up Reachability Analysis of Analog Systems. FDL (2007)
Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten
Algorithms for automatic length compensation of busses in analog integrated circuits. ISPD (2007)
Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke
Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. DAC (2007)
Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl
Robust wiring networks for DfY considering timing constraints. ACM Great Lakes Symposium on VLSI (2007)
M. Zhang, Markus Olbrich, D. Seider, M. Frerichs, Harald Kinzelbach, Erich Barke
CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. DATE (2007)
Jan Torben Weinkopf, Klaus Harbich, Erich Barke
Incremental Fault Emulation. FPL (2007)
Daniel Platte, Shangjing Jing, Ralf Sommer, Erich Barke
Ansätze zur Verbesserung der Simulationsperformance automatisch generierter analoger Verhaltensmodelle. MBMV (2006)
Daniel Platte, Shangjing Jing, Ralf Sommer, Erich Barke
Using Sequential Equations to Improve Efficiency and Robustness. FDL (2006)
Jan Torben Weinkopf, Klaus Harbich, Erich Barke
Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. FPL (2006)
Darius Grabowski, Christoph Grimm, Erich Barke
Semi-symbolic modeling and simulation of circuits and systems. ISCAS (2006)
Ralf Klausen, Lars Hedrich, Erich Barke
Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen. MBMV (2006)
Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke
Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. Electron. Notes Theor. Comput. Sci. 153 (3) (2006)
Darius Grabowski, Christoph Grimm, Erich Barke
Ein Verfahren zur effizienten Analyse von Schaltungen mit Parametervarianzen. MBMV (2006)
Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten
Routing of analog busses with parasitic symmetry. ISPD (2005)
Markus Olbrich, Erich Barke
Placement Using a Localization Probability Model (LPM). DATE (2004)
Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke
Wirelength Reduction Using 3-D Physical Design. PATMOS (2004)
Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke
Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. DATE (2004)
Andreas Hermann, Markus Olbrich, Erich Barke
Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. VLSI-SOC (2003)
Andreas Hermann, Markus Olbrich, Erich Barke
Placing substrate contacts into mixed-signal circuits controlling circuit performance. CICC (2003)
Joerg Abke, Erich Barke
A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . DATE (2002)
Andreas C. Lemke, Lars Hedrich, Erich Barke
Analog circuit sizing based on formal methods using affine arithmetic. ICCAD (2002)
Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. DATE (2002)
Walter Hartong, Lars Hedrich, Erich Barke
Model checking algorithms for analog verification. DAC (2002)
Walter Hartong, Lars Hedrich, Erich Barke
On Discrete Modeling and Model Checking for Nonlinear Analog Systems. CAV (2002)
Walter Hartong, Lars Hedrich, Erich Barke
An Approach to Model Checking for Nonlinear Analog Systems. DATE (2002)
Silke Salewski, Erich Barke
An Upper Bound for 3D Slicing Floorplans. VLSI Design (2002)
Markus Olbrich, Achim Rein, Erich Barke
An improved hierarchical classification algorithm for structural analysis of integrated circuits. DATE (2001)
Joerg Abke, Erich Barke
A New Placement Method for Direct Mapping into LUT-Based FPGAs. FPL (2001)
Joachim Küter, Erich Barke
Architecture driven partitioning. DATE (2001)
Klaus Harbich, Erich Barke
PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. FPL (2001)
Mark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch
CHIPDESIGN - A Novel Project-oriented Microelectronics Course. MSE (2001)
Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel
PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. PATMOS (2000)
Matthias Ringe, Thomas Lindenkreuz, Erich Barke
Static Timing Analysis Taking Crosstalk into Account. DATE (2000)
Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke
A current driven routing and verification methodology for analog applications. DAC (2000)
Joerg Abke, Erich Barke
CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. FPL (2000)
Thorsten Adler, Erich Barke
Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. DATE (2000)
M. Klemme, Erich Barke
An extended bipolar transistor model for substrate crosstalk analysis. CICC (1999)
Joerg Abke, Erich Barke, Jörn Stohmann
A Universal Module Generator for LUT-Based FPGAs. IEEE International Workshop on Rapid System Prototyping (1999)
Klaus Harbich, Jörn Stohmann, Erich Barke, Ludwig Schwoerer
A Case Study: Logic Emulation - Pitfalls and Solutions. IEEE International Workshop on Rapid System Prototyping (1999)
Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke
An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. FPL (1998)
Matthias Ringe, Thomas Lindenkreuz, Erich Barke
Path Verification Using Boolean Satisfiability. DATE (1998)
Lars Hedrich, Erich Barke
A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. DATE (1998)
Reza Sedaghat-Maman, Erich Barke
Real Time Fault Injection Using Logic Emulators. ASP-DAC (1998)
Reza Sedaghat-Maman, Erich Barke
A new approach to fault emulation. IEEE International Workshop on Rapid System Prototyping (1997)
Dirk Behrens, Erich Barke, Robert Tolkiehn
Design driven partitioning. ASP-DAC (1997)
Jörn Stohmann, Erich Barke
A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs. ICCD (1997)
Dirk Behrens, Klaus Harbich, Erich Barke
Hierarchical partitioning. ICCAD (1996)
Jörn Stohmann, Erich Barke
A Universal CLA Adder Generator for SRAM-Based FPGAs. FPL (1996)
Carsten Borchers, Lars Hedrich, Erich Barke
Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. DAC (1996)
Frank Scherber, Erich Barke, Wolfgang Meier
PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor. ED&TC (1996)
Lars Hedrich, Erich Barke
A formal approach to nonlinear analog circuit verification. ICCAD (1995)
Erich Barke
Line-to-ground capacitance calculation for VLSI: a comparison. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (2) (1988)
Erich Barke
Resistance calculation from mask artwork data by finite element method. DAC (1985)
Erich Barke
FERKEL: Technologieunabhängiges direktivengesteuertes Programmsystem zur Entwurfsregelnprüfung. Angew. Inform. 27 (8) (1985)
Erich Barke
A Network Comparison Algorithm for Layout Verification of Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 (2) (1984)
F. Luellau, T. Hoepken, Erich Barke
A technology independent block extraction algorithm. DAC (1984)
Erich Barke
Figurenorientierte boolesche Maskenoperationen für die Layout-Prüfung integrierter Schaltungen / Polygon-based boolean mask operations to be used in IC design rule checking. Elektron. Rechenanlagen 26 (1) (1984)
Erich Barke
A layout verification system for analog bipolar integrated circuits. DAC (1983)