Lars Hedrich

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 21

Top Venues

DATE

SMACD

ISSE

Integr.

University of Hanover (PHD)

Education History

University of Hanover

PHD

Publications

Sascha Schmalhofer, Marwin Möller, Nikoletta Katsaouni, Marcel H. Schulz, Lars Hedrich
Debugging Low Power Analog Neural Networks for Edge Computing. DATE (2023)
Nikoletta Katsaouni, Florian Aul, Lukas Krischker, Sascha Schmalhofer, Lars Hedrich, Marcel H. Schulz
Energy efficient convolutional neural networks for arrhythmia detection. Array 13 (2022)
Ahmad Tarraf, Lars Hedrich
Towards Compositional Abstraction of Analog Neuronal Networks. CCWC (2021)
Ahmad Tarraf, Lars Hedrich
From transistor level to cyber physical/hybrid systems: Formal verification using automatic compositional abstraction. it Inf. Technol. 62 (5-6) (2020)
Ahmad Tarraf, Lars Hedrich, Niklas Kochdumper, Malgorzata Rechmal-Lesse, Markus Olbrich
Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets. ISVLSI (2020)
Niklas Kochdumper, Ahmad Tarraf, Malgorzata Rechmal, Markus Olbrich, Lars Hedrich, Matthias Althoff
Establishing Reachset Conformance for the Formal Analysis of Analog Circuits. ASP-DAC (2020)
Ahmad Tarraf, Lars Hedrich
Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata. DATE (2019)
Ahmad Tarraf, Lars Hedrich
Automatic Modeling of Transistor Level Circuits by Hybrid Systems with Parameter Variable Matrices. SMACD (2019)
Yashwant Kolluru, Rolando Dölling, Lars Hedrich
Numerical Simulations of Vibro-acoustic Behaviors related to Drive Train Assemblies. ISSE (2019)
Ömer Ibrahim Erduran, Mirjam Minor, Lars Hedrich, Ahmad Tarraf, Frederik Ruehl, Hans Schroth
Multi-agent Learning for Energy-Aware Placement of Autonomous Vehicles. ICMLA (2019)
Philipp Tertel, Lars Hedrich
Real-time emulation of block-based analog circuits on an FPGA. Integr. 63 (2018)
Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Hyun-Sek Lukas Lee, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher
Novel metrics for Analog Mixed-Signal coverage. DDECS (2017)
Andreas Furtig, Moritz Paschke, Lars Hedrich
Comparing code coverage metrics for analog behavioral models. SMACD (2017)
Philipp Tertel, Lars Hedrich
Real-time emulation of block-based analog circuits on an FPGA. SMACD (2017)
Andreas Furtig, Sebastian Steinhorst, Lars Hedrich
Feature based state space coverage of analog circuits. FDL (2016)
Erich Barke, Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher
Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis. DATE (2016)
Markus Meissner, Lars Hedrich
FEATS: Framework for Explorative Analog Topology Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (2) (2015)
Felix Salfelder, Lars Hedrich
Ageing simulation of analogue circuits and systems using adaptive transient evaluation. DATE (2015)
Tim Dackermann, Rolando Dölling, Lars Hedrich
Method for system level vibro-acoustic gear modeling and simulation of electro-mechanical drive trains. ISSE (2015)
Julius von Rosen, Felix Salfelder, Lars Hedrich, Benjamin Betting, Uwe Brinkschulte
A highly dependable self-adaptive mixed-signal multi-core system-on-chip architecture. Integr. 48 (2015)
Julius von Rosen, Markus Meissner, Lars Hedrich
Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores. DATE (2015)
Mingyu Ma, Lars Hedrich, Christian Sporrer
ASDeX: a formal specification for analog circuit enabling a full automated design validation. Des. Autom. Embed. Syst. 18 (1-2) (2014)
Matthias Kauer, Swaminathan Naranayaswami, Sebastian Steinhorst, Martin Lukasiewycz, Samarjit Chakraborty, Lars Hedrich
Modular system-level architecture for concurrent cell balancing. DAC (2013)
Benjamin Betting, Julius von Rosen, Lars Hedrich, Uwe Brinkschulte
A Highly Dependable Self-adaptive Mixed-Signal Multi-core System-on-Chip. ARCS (2013)
Christoph Leineweber, Mathias Pacher, Benjamin Betting, Julius von Rosen, Uwe Brinkschulte, Lars Hedrich
Detection and Defense Strategies against Attacks on an Artificial Hormone System Running on a Mixed Signal Chip. ISORC (2012)
Sebastian Steinhorst, Lars Hedrich
Trajectory-Directed discrete state space modeling for formal verification of nonlinear analog circuits. ICCAD (2012)
Sebastian Steinhorst, Lars Hedrich
Equivalence checking of nonlinear analog circuits for hierarchical AMS System Verification. VLSI-SoC (2012)
Sebastian Steinhorst, Lars Hedrich
Analog assertion-based verification on partial state space representations using ASL. FDL (2012)
Markus Meissner, Oliver Mitea, Linda Luy, Lars Hedrich
Fast isomorphism testing for a graph-based analog circuit synthesis framework. DATE (2012)
Mingyu Ma, Lars Hedrich, Christian Sporrer
A machine-readable specification of analog circuits for integration into a validation flow. FDL (2011)
Oliver Mitea, Markus Meissner, Lars Hedrich, P. Jores
Automated constraint-driven topology synthesis for analog circuits. DATE (2011)
Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich
Design and architectures for dependable embedded systems. CODES+ISSS (2011)
Oliver Mitea, Markus Meissner, Lars Hedrich
Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts. VLSI-SoC (2011)
Sebastian Steinhorst, Lars Hedrich
Advanced methods for equivalence checking of analog circuits with strong nonlinearities. Formal Methods Syst. Des. 36 (2) (2010)
Sebastian Steinhorst, Lars Hedrich
Improving verification coverage of analog circuit blocks by state space-guided transient simulation. ISCAS (2010)
Stefan Lämmermann, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Alexander Viehl, Alexander Jesser, Lars Hedrich
Towards assertion-based verification of heterogeneous system designs. DATE (2010)
Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang
Formal approaches to analog circuit verification. DATE (2009)
Xiaoying Wang, Lars Hedrich
Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology. DATE (2008)
Alexander Jesser, Lars Hedrich
A symbolic approach for mixed-signal model checking. ASP-DAC (2008)
Alexander Jesser, Stefan Lämmermann, Alexander Pacholik, Roland Weiss, Jürgen Ruf, Lars Hedrich, Wolfgang Fengler, Thomas Kropf, Wolfgang Rosenstiel
Advanced Assertion-Based Design for Mixed-Signal Verification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Sebastian Steinhorst, Lars Hedrich
Model Checking of Analog Systems using an Analog Specification Language. DATE (2008)
Xiaoying Wang, Lars Hedrich
An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis. ASP-DAC (2006)
Xiaoying Wang, Lars Hedrich
Hierarchical exploration and selection of transistor-topologies for analog circuit design. ISCAS (2006)
Alexander Jesser, Markus Wedler, Lars Hedrich, Wolfgang Kunz
A case study on applying bounded model checking to analog circuit verification. MBMV (2006)
Ralf Klausen, Lars Hedrich, Erich Barke
Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen. MBMV (2006)
Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke
Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. Electron. Notes Theor. Comput. Sci. 153 (3) (2006)
Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke
Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. DATE (2004)
Andreas C. Lemke, Lars Hedrich, Erich Barke
Analog circuit sizing based on formal methods using affine arithmetic. ICCAD (2002)
Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. DATE (2002)
Walter Hartong, Lars Hedrich, Erich Barke
Model checking algorithms for analog verification. DAC (2002)
Walter Hartong, Lars Hedrich, Erich Barke
On Discrete Modeling and Model Checking for Nonlinear Analog Systems. CAV (2002)
Walter Hartong, Lars Hedrich, Erich Barke
An Approach to Model Checking for Nonlinear Analog Systems. DATE (2002)
Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke
A current driven routing and verification methodology for analog applications. DAC (2000)
Tim Wichmann, Ralf Popp, Walter Hartong, Lars Hedrich
On the Simplification of Nonlinear DAE Systems in Analog Circuit Design. CASC (1999)
Lars Hedrich, Erich Barke
A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. DATE (1998)
Carsten Borchers, Lars Hedrich, Erich Barke
Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. DAC (1996)
Lars Hedrich, Erich Barke
A formal approach to nonlinear analog circuit verification. ICCAD (1995)

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Publication Activity (10 Years)

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Lars Hedrich