A symbolic approach for mixed-signal model checking.
Alexander JesserLars HedrichPublished in: ASP-DAC (2008)
Keyphrases
- model checking
- mixed signal
- low power
- temporal logic
- multi channel
- formal specification
- temporal properties
- binary decision diagrams
- digital circuits
- model checker
- finite state
- formal verification
- finite state machines
- power consumption
- partial order reduction
- reachability analysis
- bounded model checking
- automated verification
- verification method
- high speed
- low cost
- epistemic logic
- symbolic model checking
- transition systems
- process algebra
- linear temporal logic
- formal methods
- model based diagnosis
- computation tree logic
- pspace complete
- symbolic representation
- concurrent systems
- asynchronous circuits
- low voltage
- alternating time temporal logic