A case study on applying bounded model checking to analog circuit verification.

Alexander Jesser Markus Wedler Lars Hedrich Wolfgang Kunz

Published in: MBMV (2006)

Keyphrases

filter bank
bounded model checking
analog circuits
formal verification
model checking
temporal logic
fault diagnosis
linear temporal logic
wavelet packet transform
multi agent systems
model checker
expert systems
real time
concurrent systems
formal specification
digital circuits
artificial intelligence