Helmut Graeb

Publication Activity (10 Years)

Years Active: 2000-2023
Publications (10 Years): 38

Top Topics

Worst Case Analysis

Reverse Engineer

Analog Circuits

Derivative Free

Top Venues

Publications

Helmut Graeb, Markus Leibl
Learning from the Implicit Functional Hierarchy in an Analog Netlist. ISPD (2023)
Inga Abel, Helmut Graeb
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition. ACM Trans. Design Autom. Electr. Syst. 27 (6) (2022)
Helmut Graeb
Analog Synthesis - The Deterministic Way. ISPD (2022)
Inga Abel, Maximilian Neuner, Helmut Graeb
A functional block decomposition method for automatic op-amp design. Integr. 85 (2022)
Inga Abel, Helmut Graeb
Structure Synthesis of Op-Amps by Functional Block Composition. CoRR (2021)
Inga Abel, Maximilian Neuner, Helmut Graeb
COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing. Integr. 76 (2021)
Grace Li Zhang, Bing Li, Xing Huang, Chen Shen, Shuhang Zhang, Florin Burcea, Helmut Graeb, Tsung-Yi Ho, Hai Li, Ulf Schlichtmann
An Efficient Programming Framework for Memristor-based Neuromorphic Computing. DATE (2021)
Maximilian Neuner, Inga Abel, Helmut Graeb
Library-free Structure Recognition for Analog Circuits. DATE (2021)
Maximilian Neuner, Helmut Graeb
Hierarchical Analog Power-Down Synthesis. ICECS (2020)
Maximilian Neuner, Helmut Graeb
Verification and revision of the power-down mode for hierarchical analog circuits. Integr. 73 (2020)
Maximilian Neuner, Helmut Graeb
Synergetic Algorithm for Power-Down Synthesis. ECCTD (2020)
Aayush Singla, Bernhard Lippmann, Helmut Graeb
Recovery of 2D and 3D Layout Information through an Advanced Image Stitching Algorithm using Scanning Electron Microscope Images. ICPR (2020)
Jahnavi Kasturi Rangan, Nasim Pour Aryan, Jens Bargfrede, Lantao Wang, Christian Funke, Helmut Graeb
Synthesis of DDRO Timing Monitors by Delay-Tracking and Static Timing Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2020)
Inga Abel, Helmut Graeb
Structural Synthesis of Operational Amplifiers Based on Functional Block Modeling. ICCAD (2020)
Alessandro Girardi, Helmut Graeb
Modeling and Optimization of a Microprobe Detector for Area and Yield Improvement. SBCCI (2020)
Inga Abel, Maximilian Neuner, Helmut Graeb
A Hierarchical Performance Equation Library for Op-Amp Design. CoRR (2020)
Inga Abel, Maximilian Neuner, Helmut Graeb
A Functional Block Decomposition Method for Automatic Op-Amp Design. CoRR (2020)
Bernhard Lippmann, Michael Werner, Niklas Unverricht, Aayush Singla, Peter Egger, Anja Dübotzky, Horst A. Gieser, Martin Rasche, Oliver Kellermann, Helmut Graeb
Integrated flow for reverse engineering of nanoscale technologies. ASP-DAC (2019)
Inga Abel, Maximilian Neuner, Helmut Graeb
Constraint-Programmed Initial Sizing of Analog Operational Amplifiers. ICCD (2019)
Samarjit Chakraborty, James H. Anderson, Martin Becker, Helmut Graeb, Samiran Halder, Ravindra Metta, Lothar Thiele, Stavros Tripakis, Anand Yeolekar
Cross-Layer Interactions in CPS for Performance and Certification. DATE (2019)
Florin Burcea, Helmut Graeb
Inversion-Coefficient-Aware Yield Optimization of Analog Circuits. ICECS (2019)
Sebastian Kiesel, Thomas Kern, Bernhard Wicht, Helmut Graeb
A 30 ns 16 Mb 2 b/cell Embedded Flash with Ramped Gate Time-Domain Sensing Scheme for Automotive Application. VLSI-DAT (2019)
Maximilian Neuner, Helmut Graeb
Power-Down Mode Verification for Hierarchical Analog Circuits. SMACD (2019)
Florin Burcea, Andreas Herrmann, Bing Li, Helmut Graeb
MEMS-IC Robustness Optimization Considering Electrical and Mechanical Design and Process Parameters. ACM Trans. Design Autom. Electr. Syst. 24 (4) (2019)
Aayush Singla, Bernhard Lippmann, Helmut Graeb
Verification of Physical Chip Layouts Using GDSII Design Data. IVSW (2019)
Vittorio Latorre, Husni M. Habal, Helmut Graeb, Stefano Lucidi
Derivative free methodologies for circuit worst case analysis. Optim. Lett. 13 (7) (2019)
Jahnavi Kasturi Rangan, Nasim Pour Aryan, Lantao Wang, Jens Bargfrede, Christian Funke, Helmut Graeb
Design-dependent Monitors Based on Delay Sensitivity Tracking. ICECS (2018)
Andreas Herrmann, Michael Weiner, Michael Pehl, Helmut Graeb
Bringing Analog Design Tools to Security: Modeling and Optimization of a Low Area Probing Detector. SMACD (2018)
Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann
On enabling diagnosis for 1-Pin Test fails in an industrial flow. ASP-DAC (2018)
Florin Burcea, Andreas Herrmann, Bing Li, Helmut Graeb
MEMS-IC Optimization Considering Design Parameters and Manufacturing Variation from both Mechanical and Electrical Side. ICECS (2018)
Francesco Santoro, Rüdiger Kuhn, Neil Gibson, Nicola Rasera, Thomas Tost, Helmut Graeb, Bernhard Wicht, Ralf Brederlow
A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications. IEEE J. Solid State Circuits 53 (6) (2018)
Florin Burcea, Andreas Herrmann, Aditya Gupta, Helmut Graeb
A new robustness optimization methodology for MEMS-IC systems. SMACD (2017)
Michael Zwerger, Maximilian Neuner, Helmut Graeb
Analog Power-Down Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (12) (2017)
Pang-Yen Chou, Nai-Chen Chen, Mark Po-Hung Lin, Helmut Graeb
Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters. IEEE Trans. Very Large Scale Integr. Syst. 25 (8) (2017)
Andreas Herrmann, Christof Hielscher, Alexander Mueller, Gisbert Hoelzer, Helmut Graeb
Realistic worst-case parameter sets for MEMS technologies. SMACD (2017)
Michael Zwerger, Gaurav Shrivastava, Helmut Graeb
Power-down synthesis for analog circuits including switch sizing. SMACD (2016)
Husni M. Habal, Helmut Graeb
A step-accurate model for the trapping and release of charge carriers suitable for the transient simulation of analog circuits. Microelectron. Reliab. 61 (2016)
Michael Pehl, Matthias Hiller, Helmut Graeb
Efficient Evaluation of Physical Unclonable Functions Using Entropy Measures. J. Circuits Syst. Comput. 25 (1) (2016)
Chia-Yu Wu, Helmut Graeb, Jiang Hu
A pre-search assisted ILP approach to analog integrated circuit routing. ICCD (2015)
Michael Zwerger, Pantelis-Rafail Vlachas, Helmut Graeb
A fast analytical approach for static power-down mode analysis. ICECS (2015)
Michael Pehl, Akshara Ranjit Punnakkal, Matthias Hiller, Helmut Graeb
Advanced performance metrics for Physical Unclonable Functions. ISIC (2014)
Helmut Graeb
ITRS 2011 Analog EDA Challenges and Approaches. DATE (2012)
Xin Pan, Helmut Graeb
Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area. Microelectron. Reliab. 52 (8) (2012)
Husni M. Habal, Helmut Graeb
Constraint-Based Layout-Driven Sizing of Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (8) (2011)
Xin Pan, Helmut Graeb
Reliability analysis of analog circuits by lifetime yield prediction using worst-case distance degradation rate. ISQED (2010)
Xin Pan, Helmut Graeb
Reliability analysis of analog circuits using quadratic lifetime worst-case distance prediction. CICC (2010)
Daniel Mueller-Gritschneder, Helmut Graeb
Computation of yield-optimized Pareto fronts for analog integrated circuit specifications. DATE (2010)
Helmut Graeb, Daniel Mueller-Gritschneder, Ulf Schlichtmann
Pareto optimization of analog circuits considering variability. Int. J. Circuit Theory Appl. 37 (2) (2009)
Xin Pan, Helmut Graeb
Degradation-aware analog design flow for lifetime yield analysis and optimization. ICECS (2009)
Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang
Formal approaches to analog circuit verification. DATE (2009)
Engin Avci, Martin Strasser, Helmut Graeb, Ulf Schlichtmann
A free-shape router for analog and RF applications. ECCTD (2009)
Jun Zou, Helmut Graeb, Daniel Mueller, Ulf Schlichtmann
Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts. CICC (2007)
Helmut Graeb, Daniel Mueller, Ulf Schlichtmann
Pareto optimization of analog circuits considering variability. ECCTD (2007)
Frank Schenkel, Michael Pronath, Helmut Graeb, Kurt Antreich
A fast method for identifying matching-relevant transistor pairs. CICC (2001)
Kurt Antreich, Josef Eckmüller, Helmut Graeb, Michael Pronath, Frank Schenkel, Robert Schwencker, Stephan Zizala
WiCkeD: analog circuit synthesis incorporating mismatch. CICC (2000)