Horst A. Gieser

Publication Activity (10 Years)

Years Active: 2003-2022
Publications (10 Years): 5

Top Topics

Conceptual Schema

Software Product

Reverse Engineer

Top Venues

IACR Trans. Cryptogr. Hardw. Embed. Syst.

IACR Cryptol. ePrint Arch.

Publications

Bernhard Lippmann, Ann-Christin Bette, Matthias Ludwig, Johannes Mutter, Johanna Baehr, Alexander Hepp, Horst A. Gieser, Nicola Kovac, Tobias Zweifel, Martin Rasche, Oliver Kellermann
Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions. DATE (2022)
Johann Heyszl, Katja Miller, Florian Unterstein, Marc Schink, Alexander Wagner, Horst A. Gieser, Sven Freud, Tobias Damm, Dominik Klein, Dennis Kügler
Investigating Profiled Side-Channel Attacks Against the DES Key Schedule. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020 (3) (2020)
Bernhard Lippmann, Niklas Unverricht, Aayush Singla, Matthias Ludwig, Michael Werner, Peter Egger, Anja Dübotzky, Helmut Gräb, Horst A. Gieser, Martin Rasche, Oliver Kellermann
Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies. Integr. 71 (2020)
Bernhard Lippmann, Michael Werner, Niklas Unverricht, Aayush Singla, Peter Egger, Anja Dübotzky, Horst A. Gieser, Martin Rasche, Oliver Kellermann, Helmut Graeb
Integrated flow for reverse engineering of nanoscale technologies. ASP-DAC (2019)
Johann Heyszl, Katja Miller, Florian Unterstein, Marc Schink, Alexander Wagner, Horst A. Gieser, Sven Freud, Tobias Damm, Dominik Klein, Dennis Kügler
Investigating Profiled Side-Channel Attacks Against the DES Key Schedule. IACR Cryptol. ePrint Arch. 2019 (2019)
Tekfouy Lim, Horst A. Gieser, Luca Santarelli, Franco Cacialli
Electrostatic discharge sensitivity investigation on organic field-effect thin film transistors. NEWCAS (2015)
Heinrich Wolf, Horst A. Gieser, Dirk Walter
Investigating the CDM susceptibility of IC's at package and wafer level by capacitive coupled TLP. Microelectron. Reliab. 49 (12) (2009)
M. Etherton, Ning Qu, J. Willemen, Wolfgang Wilkening, S. Mettler, Mariano Dissegna, R. Stella, L. Zullino, A. Andreini, Horst A. Gieser
Study of CDM specific effects for a smart power input protection structure. Microelectron. Reliab. 46 (5-6) (2006)
Detlef Bonfert, Horst A. Gieser, Heinrich Wolf, M. Frank, A. Konrad, J. Schulz
Transient-induced latch-up test setup for wafer-level and package-level. Microelectron. Reliab. 46 (9-11) (2006)
Heinrich Wolf, Horst A. Gieser, Detlef Bonfert, Markus Hauser
ESD Susceptibility of Submicron Air Gaps. Microelectron. Reliab. 46 (9-11) (2006)
Heinrich Wolf, Horst A. Gieser, Wolfgang Soldner, Harald Gossner
A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits. Microelectron. Reliab. 45 (9-11) (2005)
S. Bargstädt-Franke, Wolfgang Stadler, Kai Esmark, Martin Streibl, Krzysztof Domanski, Horst A. Gieser, Heinrich Wolf, Waclaw Bala
Transient latch-up: experimental analysis and device simulation. Microelectron. Reliab. 45 (2) (2005)
Heinrich Wolf, Horst A. Gieser, Wolfgang Stadler, Wolfgang Wilkening
Capacitively coupled transmission line pulsing cc-TLP--a traceable and reproducible stress method in the CDM-domain. Microelectron. Reliab. 45 (2) (2005)
Horst A. Gieser
On-chip electrostatic discharge ESD. Microelectron. Reliab. 43 (7) (2003)