Time Constrained Verification of Analog Circuits using Model-Checking Algorithms.
Darius GrabowskiDaniel PlatteLars HedrichErich BarkePublished in: Electron. Notes Theor. Comput. Sci. (2006)
Keyphrases
- model checking
- formal verification
- temporal logic
- verification method
- model checker
- automated verification
- reachability analysis
- concurrent systems
- deterministic finite automaton
- temporal properties
- orders of magnitude
- finite state
- formal methods
- formal specification
- process algebra
- symbolic model checking
- analog circuits
- computational complexity
- partial order reduction
- bounded model checking
- pspace complete
- graph theory
- knowledge base
- timed automata
- transition systems
- artificial intelligence
- epistemic logic
- np complete
- computation tree logic