Kanupriya Gulati

Publication Activity (10 Years)

Years Active: 2005-2013
Publications (10 Years): 0

Top Topics

Computational Cost

Computationally Expensive

Memory Requirements

Top Venues

Publications

John F. Croix, Sunil P. Khatri, Kanupriya Gulati
Using GPUs to Accelerate CAD Algorithms. IEEE Des. Test 30 (1) (2013)
Kanupriya Gulati, Sunil P. Khatri
Fault Table Computation on GPUs. J. Electron. Test. 26 (2) (2010)
Kanupriya Gulati, Sunil P. Khatri
Boolean satisfiability on a graphics processor. ACM Great Lakes Symposium on VLSI (2010)
Kanupriya Gulati, Sunil P. Khatri, Peng Li
Closed-loop modeling of power and temperature profiles of FPGAs. FPGA (2009)
Kanupriya Gulati, Sunil P. Khatri
Accelerating statistical static timing analysis using graphics processing units. ASP-DAC (2009)
Jeff L. Cobb, Kanupriya Gulati, Sunil P. Khatri
Robust window-based multi-node technology-independent logic minimization. ACM Great Lakes Symposium on VLSI (2009)
Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
On-chip bidirectional wiring for heavily pipelined systems using network coding. ICCD (2009)
Srikanth Alaparthi, Kanupriya Gulati, Sunil P. Khatri
Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation. ISCAS (2009)
Kalyana C. Bollapalli, Yiyue Wu, Kanupriya Gulati, Sunil Khatri, A. Robert Calderbank
Highly parallel decoding of space-time codes on graphics processing units. Allerton (2009)
Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
Selective Forward Body Bias for High Speed and Low Power SRAMs. J. Low Power Electron. 5 (2) (2009)
Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry
Fast circuit simulation on graphics processing units. ASP-DAC (2009)
Kanupriya Gulati, Sunil P. Khatri
Fault table generation using Graphics Processing Units. HLDVT (2009)
Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
Low power and high performance sram design using bank-based selective forward body bias. ACM Great Lakes Symposium on VLSI (2009)
Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas
FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14 (2) (2009)
Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integr. 41 (3) (2008)
Kanupriya Gulati, Mandar Waghmode, Sunil P. Khatri, Weiping Shi
Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. IET Comput. Digit. Tech. 2 (3) (2008)
Kanupriya Gulati, Sunil P. Khatri
Improving FPGA routability using network coding. ACM Great Lakes Symposium on VLSI (2008)
Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri
SAT-based ATPG using multilevel compatible don't-cares. ACM Trans. Design Autom. Electr. Syst. 13 (2) (2008)
Kanupriya Gulati, Sunil P. Khatri
Towards acceleration of fault simulation using graphics processing units. DAC (2008)
Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
A Structured ASIC Design Approach Using Pass Transistor Logic. ISCAS (2007)
Eugene Goldberg, Kanupriya Gulati
On Complexity of Internal and External Equivalence Checking. DSD (2007)
Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri
Toggle Equivalence Preserving (TEP) Logic Optimization. DSD (2007)
Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri
Controlling inductive cross-talk and power in off-chip buses using CODECs. ASP-DAC (2006)
Kanupriya Gulati, M. Lovell, Sunil P. Khatri
Efficient don't care computation for hierarchical designs. ISCAS (2006)
Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
A probabilistic method to determine the minimum leakage vector for combinational designs. ISCAS (2006)
Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri
Memory-based crosstalk canceling CODECs for on-chip buses. ISCAS (2006)
Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson
Network coding for routability improvement in VLSI. ICCAD (2006)
Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri
A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI (2006)
Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi
An Efficient, Scalable Hardware Engine for Boolean SATisfiability. ICCD (2006)
Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri
An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. ISLPED (2005)