FPGA-based hardware acceleration for Boolean satisfiability.
Kanupriya GulatiSuganth PaulSunil P. KhatriSrinivas PatilAbhijit JasPublished in: ACM Trans. Design Autom. Electr. Syst. (2009)
Keyphrases
- boolean satisfiability
- hardware architecture
- hardware implementation
- probabilistic planning
- field programmable gate array
- integer linear programming
- sat solvers
- boolean optimization
- sat solving
- sat problem
- branch and bound algorithm
- randomly generated
- symmetry breaking
- maximum satisfiability
- max sat
- phase transition
- heuristic search
- np complete
- sat instances
- branch and bound
- combinatorial problems
- genetic algorithm
- special case
- random sat instances
- search algorithm