Rajesh Garg

Publication Activity (10 Years)

Years Active: 2006-2012
Publications (10 Years): 0

Top Topics

Information Security Management

Autonomic Computing

Business Process

Top Venues

Publications

Hai Huang, Salman Baset, Chunqiang Tang, Ashu Gupta, K. N. Madhu Sudhan, Fazal Feroze, Rajesh Garg, Sumithra Ravichandran
Patch management automation for enterprise cloud. NOMS (2012)
Vinay Karkala, Kalyana C. Bollapalli, Rajesh Garg, Sunil P. Khatri
A PLL design based on a standing wave resonant oscillator. ICCD (2009)
Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya
Design and implementation of a sub-threshold BFSK transmitter. ISQED (2009)
Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
On-chip bidirectional wiring for heavily pipelined systems using network coding. ICCD (2009)
Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi
SEU hardened clock regeneration circuits. ISQED (2009)
Rajesh Garg, Sunil P. Khatri
Efficient analytical determination of the SEU-induced pulse shape. ASP-DAC (2009)
Rajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri
A robust pulsed flip-flop and its use in enhanced scan design. ICCD (2009)
Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
Selective Forward Body Bias for High Speed and Low Power SRAMs. J. Low Power Electron. 5 (2) (2009)
Rajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal, Sunil P. Khatri
A radiation tolerant Phase Locked Loop design for digital electronics. ICCD (2009)
Rajesh Garg, Sunil P. Khatri
3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit. ICCD (2009)
Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
Low power and high performance sram design using bank-based selective forward body bias. ACM Great Lakes Symposium on VLSI (2009)
Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi
Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. IEEE Trans. Very Large Scale Integr. Syst. 17 (6) (2009)
Sasidharan Ekambavanan, Rajesh Garg, Sunil P. Khatri, Krishna R. Narayanan
Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization. J. Low Power Electron. 5 (2) (2009)
Charu Nagpal, Rajesh Garg, Sunil P. Khatri
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. DATE (2008)
Suganth Paul, Rajesh Garg, Sunil P. Khatri
Pipelined network of PLA based circuit design. ACM Great Lakes Symposium on VLSI (2008)
Rajesh Garg, Peng Li, Sunil P. Khatri
Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). ISCAS (2008)
Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri
A Single-supply True Voltage Level Shifter. DATE (2008)
Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri
A robust, fast pulsed flip-flop design. ACM Great Lakes Symposium on VLSI (2008)
Rajesh Garg, Charu Nagpal, Sunil P. Khatri
A fast, analytical estimator for the SEU-induced pulse width in combinational designs. DAC (2008)
Rajesh Garg, Sunil P. Khatri
A novel, highly SEU tolerant digital circuit design approach. ICCD (2008)
Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng
A lithography-friendly structured ASIC design approach. ACM Great Lakes Symposium on VLSI (2008)
Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri
A methodology for interconnect dimension determination. ISPD (2007)
Rajesh Garg, Chunjie Duan, Jinyun Zhang, Sinan Gezici
Low Power UWB Transceiver Design Using Dynamic Voltage Scaling. WCNC (2007)
Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri
On the Improvement of Statistical Static Timing Analysis. ICCD (2006)
Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri
CMOS Comparators for High-Speed and Low-Power Applications. ICCD (2006)
Rajesh Garg, Sunil P. Khatri
Generalized buffering of PTL logic stages using Boolean division. ISCAS (2006)
Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi
A design approach for radiation-hard digital electronics. DAC (2006)
Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri
A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI (2006)
Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri
A PLA based asynchronous micropipelining approach for subthreshold circuit design. DAC (2006)