Mihir R. Choudhury

Publication Activity (10 Years)

Years Active: 2005-2021
Publications (10 Years): 5

Top Topics

Functional Decomposition

Error Resilience

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Ruchir Puri, David S. Kung, Geert Janssen, Wei Zhang, Giacomo Domeniconi, Vladimir Zolotov, Julian Dolby, Jie Chen, Mihir R. Choudhury, Lindsey Decker, Veronika Thost, Luca Buratti, Saurabh Pujar, Shyam Ramji, Ulrich Finkler, Susan Malaika, Frederick Reiss
CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks. NeurIPS Datasets and Benchmarks (2021)
Ruchir Puri, David S. Kung, Geert Janssen, Wei Zhang, Giacomo Domeniconi, Vladimir Zolotov, Julian Dolby, Jie Chen, Mihir R. Choudhury, Lindsey Decker, Veronika Thost, Luca Buratti, Saurabh Pujar, Ulrich Finkler
Project CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks. CoRR (2021)
Atin Sood, Benjamin Elder, Benjamin Herta, Chao Xue, Costas Bekas, A. Cristiano I. Malossi, Debashish Saha, Florian Scheidegger, Ganesh Venkataraman, Gegi Thomas, Giovanni Mariani, Hendrik Strobelt, Horst Samulowitz, Martin Wistuba, Matteo Manica, Mihir R. Choudhury, Rong Yan, Roxana Istrate, Ruchir Puri, Tejaswini Pedapati
NeuNetS: An Automated Synthesis Engine for Neural Network Design. CoRR (2019)
Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (5) (2016)
Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs. ASP-DAC (2015)
Ruchir Puri, Mihir R. Choudhury, Haifeng Qian, Matthew M. Ziegler
Bridging high performance and low power in processor design. ISLPED (2014)
Mihir R. Choudhury, Vikas Chandra, Robert C. Aitken, Kartik Mohanram
Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience. IEEE Trans. Computers 63 (2) (2014)
Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (10) (2014)
Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. DAC (2013)
Mihir R. Choudhury, Kartik Mohanram
Low Cost Concurrent Error Masking Using Approximate Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (8) (2013)
Andrew Zukoski, Mihir R. Choudhury, Kartik Mohanram
Reliability-driven don't care assignment for logic synthesis. DATE (2011)
Mihir R. Choudhury, Kartik Mohanram
Bi-decomposition of large Boolean functions using blocking edge graphs. ICCAD (2010)
Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken
Analytical model for TDDB-based performance degradation in combinational logic. DATE (2010)
Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram
Dominant critical gate identification for power and yield optimization in logic circuits. ACM Great Lakes Symposium on VLSI (2010)
Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken
TIMBER: Time borrowing and error relaying for online timing error resilience. DATE (2010)
Mihir R. Choudhury, Kartik Mohanram
Masking timing errors on speed-paths in logic circuits. DATE (2009)
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion. J. Electron. Test. 25 (2-3) (2009)
Mihir R. Choudhury, Kartik Mohanram
Timing-driven optimization using lookahead logic circuits. DAC (2009)
Mihir R. Choudhury, Kartik Mohanram
Reliability Analysis of Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (3) (2009)
Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram
Technology exploration for graphene nanoribbon FETs. DAC (2008)
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits. ETS (2008)
Mihir R. Choudhury, Kartik Mohanram
Approximate logic circuits for low overhead, non-intrusive concurrent error detection. DATE (2008)
Mihir R. Choudhury, Kartik Mohanram
Accurate and scalable reliability analysis of logic circuits. DATE (2007)
Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram
Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. DATE (2007)
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
Design Optimization for Robustness to Single Event Upsets. VTS (2006)
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. ICCAD (2006)
Saurabh Goyal, Mihir R. Choudhury, S. S. S. P. Rao, L. Kalyan Kumar
Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs. VLSI Design (2005)