Subhendu Roy

Publication Activity (10 Years)

Years Active: 2010-2022
Publications (10 Years): 10

Top Topics

Design Space Exploration

Machine Learning

Operating Conditions

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Hao Geng, Yuzhe Ma, Qi Xu, Jin Miao, Subhendu Roy, Bei Yu
High-Speed Adder Design Space Exploration via Graph Neural Processes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (8) (2022)
Urmimala Roy, Tanmoy Pramanik, Subhendu Roy, Avhishek Chatterjee, Leonard F. Register, Sanjay K. Banerjee
Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory. ACM Trans. Design Autom. Electr. Syst. 26 (3) (2021)
Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu
Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (12) (2019)
Jin Miao, Meng Li, Subhendu Roy, Yuzhe Ma, Bei Yu
SD-PUF: Spliced Digital Physical Unclonable Function. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (5) (2018)
Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu
Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach. CoRR (2018)
Subhendu Roy, Yuzhe Ma, Jin Miao, Bei Yu
A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders. ISLPED (2017)
Jin Miao, Meng Li, Subhendu Roy, Bei Yu
LRR-DPUF: learning resilient and reliable digital physical unclonable function. ICCAD (2016)
Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan
Design for manufacturability and reliability in extreme-scaling VLSI. Sci. China Inf. Sci. 59 (6) (2016)
Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (5) (2016)
Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, David Z. Pan
OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (10) (2016)
Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs. ASP-DAC (2015)
Subhendu Roy, Derong Liu, Junhyung Um, David Z. Pan
OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions. DAC (2015)
Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen
CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction. ICCD (2015)
Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet
Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. ACM Great Lakes Symposium on VLSI (2015)
Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan
Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (4) (2015)
Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan
Clock tree resynthesis for multi-corner multi-mode timing closure. ISPD (2014)
Bei Yu, Subhendu Roy, Jhih-Rong Gao, David Z. Pan
Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session). CoRR (2014)
Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (10) (2014)
Subhendu Roy, David Z. Pan
Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown. VLSI Design (2014)
Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. DAC (2013)
Subhendu Roy, Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar
Large Scale VLSI Circuit Simulation Using Point Relaxation. CSC (2010)