Laurent Masse-Navette

Publication Activity (10 Years)

Years Active: 1991-2019
Publications (10 Years): 2

Top Topics

Tree Structures

Power Consumption

Incremental Version

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ACM Great Lakes Symposium on VLSI

Publications

Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery
Timing-Driven and Placement-Aware Multibit Register Composition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (8) (2019)
Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. DAC (2017)
Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet
Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. ACM Great Lakes Symposium on VLSI (2015)
Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan
Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (4) (2015)
Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan
Clock tree resynthesis for multi-corner multi-mode timing closure. ISPD (2014)
J. Quali, Gabriele Saucier, P. Y. Alla, Jacques Trilhe, Laurent Masse-Navette
A Customizable Neural Processor for Distributed Neural Network. VLSI (1991)