Gabriele Saucier

Publication Activity (10 Years)

Years Active: 1972-2002
Publications (10 Years): 0

Publications

Vassilios Gerousis, Oz Levia, Pierre G. Paulin, Mark Pinto, Chris Rowen, Gabriele Saucier
Who Owns the Platform? DATE (2002)
L. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, Gabriele Saucier
E-Design Based on the Reuse Paradigm. DATE (2002)
Helena Krupnova, Gabriele Saucier
FPGA-Based Emulation: Industrial and Custom Prototyping Solutions. FPL (2000)
Helena Krupnova, Gabriele Saucier
FPGA Technology Snapshot: Current Devices and Design Tools. IEEE International Workshop on Rapid System Prototyping (2000)
Helena Krupnova, Gabriele Saucier
Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs. DATE (1999)
Helena Krupnova, Gabriele Saucier
Hierarchical Interactive Approach to Partition Large Designs into FPGAs. FPL (1999)
Helena Krupnova, Christian Rabedaoro, Gabriele Saucier
FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study. IEEE International Workshop on Rapid System Prototyping (1999)
Helena Krupnova, Gabriele Saucier
Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks. FPGA (1999)
Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier
A Knowledge-Based System for Prototyping on FPFAs. FPL (1998)
Helena Krupnova, B. Behnam, Gabriele Saucier
Block and IP Wrapping for Efficient Design on FPGAs (Abstract). FPGA (1998)
Bernard Laurent, Gilles Bosco, Gabriele Saucier
Fast Arithmetic on Xilinx 5200 FPGA. VLSI Design (1998)
S. A. Senouci, Aadil Amoura, Helena Krupnova, Gabriele Saucier
Timing Driven Floorplanning on Programmable Hierarchical Targets. FPGA (1998)
Daniel R. Brasen, Gabriele Saucier
Using cone structures for circuit partitioning into FPGA packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (7) (1998)
Helena Krupnova, D. D. A. Vu, Gabriele Saucier, M. Boubal
Real Time Prototyping Method and a Case Study. International Workshop on Rapid System Prototyping (1998)
Helena Krupnova, Christian Rabedaoro, Gabriele Saucier
Synthesis and Floorplanning for Large Hierarchical FPGAs. FPGA (1997)
Helena Krupnova, Ali Abbara, Gabriele Saucier
A Hierarchy-Driven FPGA Partitioning Method. DAC (1997)
Bernard Laurent, Gilles Bosco, Gabriele Saucier
Structural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGA. FPL (1997)
P. Brahic, Régis Leveugle, Gabriele Saucier
Design of defect-tolerant scan chains for MCMs with an active substrate. DFT (1995)
Raphaël Rochet, Régis Leveugle, Gabriele Saucier
Efficient synthesis of fault-tolerant controllers. ED&TC (1995)
C. Safinia, Régis Leveugle, Gabriele Saucier
Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. EDAC-ETC-EUROASIC (1994)
Daniel R. Brasen, Gabriele Saucier
FPGA Partitioning for Critical Paths. EDAC-ETC-EUROASIC (1994)
Régis Leveugle, Zahava Koren, Israel Koren, Gabriele Saucier, Norbert Wehn
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis. IEEE Trans. Computers 43 (12) (1994)
D. Jacquet, Gabriele Saucier
Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural Network. EDAC-ETC-EUROASIC (1994)
T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier
Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. EDAC-ETC-EUROASIC (1994)
Kella Knack, Gordan Hyland, Jim Jasmin, John Frediani, Tom Reiner, Steven Trimberger, Gabriele Saucier
Design Automation Tools for FPGA Design (Panel). DAC (1994)
Régis Leveugle, Raphaël Rochet, Gabriele Saucier
Alternative Approaches to Fault Detection in FSMs. DFT (1994)
Raphaël Rochet, Régis Leveugle, Gabriele Saucier
Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. DFT (1993)
Margot Karam, Gabriele Saucier
Functional versus random test generation for sequential circuits. J. Electron. Test. 4 (1) (1993)
Régis Leveugle, X. Delord, Gabriele Saucier
Influence of Error Correlations on the Signature Analysis Aliasing. ICCD (1993)
Gabriele Saucier, Daniel R. Brasen, J. P. Hiol
Partitioning with cone structures. ICCAD (1993)
Pierre Abouzeid, Belgacem Babba, Michel Crastes de Paulet, Gabriele Saucier
Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (7) (1993)
Gabriele Saucier, Pierre Abouzeid
Lexicographical expressions of Boolean functions with application to multilevel synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (11) (1993)
D. Jacquet, Gabriele Saucier
Design of a dedicated neural network on silicon: application to optical character recognition. VLSI (1993)
Régis Leveugle, Raphaël Rochet, Gabriele Saucier, L. Martinez, C. Pitot
A Synthesis Tool for Fault-Tolerant Finite State Machines. FTCS (1993)
Pierre Abouzeid, Régis Leveugle, Gabriele Saucier
Logic Synthesis for Automatic Layout. Synthesis for Control Dominated Circuits (1992)
Ahmed Boubekeur, Jean-Luc Patry, Gabriele Saucier, Jacques Trilhe
Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors. Computer 25 (4) (1992)
Laurent Gerbaux, Gabriele Saucier
Automatic synthesis of large Moore sequencers. Integr. 13 (3) (1992)
Anne Mignotte, Marie-Claude Bertrand, Michel Crastes de Paulet, Jérôme Rampon, Gabriele Saucier
ASYL: A Control Driven RTL Synthesis System using Library Blocks. Synthesis for Control Dominated Circuits (1992)
T. Besson, H. Bouzouzou, M. Crastes, Ion Floricica, Gabriele Saucier
Synthesis on Multiplexer-Based F.P.G.A. Using Binary Decision Diagrams. ICCD (1992)
H. Belhadj, Laurent Gerbaux, Marie-Claude Bertrand, Gabriele Saucier
Specification and Synthesis of Communicating Finite State Machines. Synthesis for Control Dominated Circuits (1992)
Laurent Gerbaux, Régis Leveugle, Gabriele Saucier
Synthesis of large controllers using ROM or PLA generators. Synthesis for Control Dominated Circuits (1992)
Margot Karam, Régis Leveugle, Gabriele Saucier
Hierarchical Test Generation Based on Delayed Propagation. ITC (1991)
T. Michel, Régis Leveugle, Gabriele Saucier
A New Approach to Control Flow Checking Without Program Modification. FTCS (1991)
Christopher Duff, Gabriele Saucier
State Assignment Based on the Reduced Dependency Theory and Recent Experimental Results. ICCAD (1991)
M. Crastes, K. Sakouti, Gabriele Saucier
A Technology Mapping Method Based On Perfect And Semi-Perfect Matchings. DAC (1991)
X. Delord, Gabriele Saucier
Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Multiprocessors. ITC (1991)
J. Quali, Gabriele Saucier, P. Y. Alla, Jacques Trilhe, Laurent Masse-Navette
A Customizable Neural Processor for Distributed Neural Network. VLSI (1991)
Régis Leveugle, T. Michel, Gabriele Saucier
Design of microprocessors with built-in on-line test. FTCS (1990)
Gabriele Saucier, Pascal Sicard, Laurent Bouchet
Multi-level synthesis on PALs. EURO-DAC (1990)
Gabriele Saucier, Christopher Duff, Franck Poirot
State assignment of controllers for optimal area implementation. EURO-DAC (1990)
J. Ouali, Gabriele Saucier
Silicon compiler for neuro-ASICs. IJCNN (1990)
Régis Leveugle, Gabriele Saucier
Optimized Synthesis of Concurrently Checked Controllers. IEEE Trans. Computers 39 (4) (1990)
Pierre Abouzeid, K. Sakouti, Gabriele Saucier, Franck Poirot
Multilevel Synthesis Minimizing the Routing Factor. DAC (1990)
Gabriele Saucier, Christopher Duff, Franck Poirot
State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory. DAC (1989)
Michel Crastes de Paulet, Margot Karam, Gabriele Saucier
Testability Expertise and Test Planning from High-Level Specifications. ITC (1989)
Régis Leveugle, Gabriele Saucier
Concurrent checking in dedicated controllers. ICCD (1989)
Régis Leveugle, Gabriele Saucier
Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. ITC (1989)
Gabriele Saucier, Régis Leveugle, Pierre Abouzeid
A channelless layout for multilevel synthesis with compiled cells. ICCD (1989)
J. Ouali, Gabriele Saucier
A flexible architecture for neural networks. ICCD (1989)
Manfred Glesner, M. Huch, Peter A. Ivey, T. Midwinter, Gabriele Saucier, Jacques Trilhe
Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung. GI Jahrestagung (2) (1988)
Ghislaine Thuau, Gabriele Saucier
Optimized Layout of MOS Cells. IEEE Trans. Computers 37 (1) (1988)
E. F. M. Kouka, Gabriele Saucier
An Application of Exploratory Data Analysis Techniques to Floorplan Design. DAC (1987)
Gabriele Saucier, Michel Crastes de Paulet, Pascal Sicard
ASYL: A Rule-Based System for Controller Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (6) (1987)
E. Dupont, Jeanne Idt, Gabriele Saucier
A Rule-Based System for the Optimal State Assignment of Controllers. FJCC (1986)
Gabriele Saucier, Ghislaine Thuau
Systematic and optimized layout of MOS cells. DAC (1985)
Gabriele Saucier, Catherine Bellon
VLSI test expertise system using a control flow model. DAC (1984)
Robert Cuykendall, Antun Domic, William H. Joyner, Stephen C. Johnson, Steven H. Kelem, Dennis McBride, Jack Mostow, John E. Savage, Gabriele Saucier
Design synthesis in VLSI and software engineering. J. Syst. Softw. 4 (1) (1984)
Catherine Bellon, Gabriele Saucier
CADOC : A System for Computer Aided Functional Test. ITC (1984)
Catherine Bellon, Gabriele Saucier
Protection Against External Errors in a Dedicated System. IEEE Trans. Computers 31 (4) (1982)
Catherine Bellon, A. Liothin, Sylvain Sadier, Gabriele Saucier, Raoul Velazco, Francois Grillot, M. Issenman
Automatic generation of microprocessor test programs. DAC (1982)
Philippe Basset, Gabriele Saucier
Top down design and testability of VLSI circuits. DAC (1982)
Catherine Bellon, Gabriele Saucier, José-Maria Gobbi
Hardware description levels and test for complex circuits. DAC (1981)
Chantal Robach, Gabriele Saucier
Dynamic Testing of Control Units. IEEE Trans. Computers 27 (7) (1978)
M. Moalla, Gabriele Saucier, Joseph Sifakis, Marianthi Zachariades
A Design Tool for the Multilevel Description and Simulation of Systems of Interconnected Modules. ISCA (1976)
Chantal Robach, Gabriele Saucier, J. Lebrun
Processor Testability and Design Consequences. IEEE Trans. Computers 25 (6) (1976)
Bernard Courtois, Gabriele Saucier
On balancing hardware-firmware for designing a fault-tolerant computers' series. MICRO (2) (1975)
Chantal Robach, Gabriele Saucier
Diversified Test Methods for Local Control Units. IEEE Trans. Computers 24 (5) (1975)
Gabriele Saucier
Next-State Equations of Asynchronous Sequential Machines. IEEE Trans. Computers 21 (4) (1972)
Gabriele Saucier
State Assignment of Asynchronous Sequential Machines Using Graph Techniques. IEEE Trans. Computers 21 (3) (1972)