Synthesis for Control Dominated Circuits

Keyphrases

Publications

1993

Synthesis for Control Dominated Circuits, Selected papers from the IFIP WG10.2/WG10.5 Workshops, Grenoble, France, April and September, 1992 Synthesis for Control Dominated Circuits (1993)

1992

Eric Gautrin, Laurent Perraudeau
MADMACS: an environment for the layout of regular arrays. Synthesis for Control Dominated Circuits (1992)
H. Zhang, Kunihiro Asada
A general and efficient mask pattern generator for non-series-parallel CMOS transistor network. Synthesis for Control Dominated Circuits (1992)
E. T. Kapuya, M. D. Edwards
Microarchitecture/Microcode Synthesis from VHDL. Synthesis for Control Dominated Circuits (1992)
C. Safina, Régis Leveugle
Clocking scheme selection for circuits made up of a controller and a datapath. Synthesis for Control Dominated Circuits (1992)
Jochen Beister, Ralf Wollowski
Controller Implementation by Communicating Asynchronous Sequential Circuits Generated from a Petri Net Specification of Required Behavior. Synthesis for Control Dominated Circuits (1992)
Evagelos Katsadas, Zohair Sahraoui, Maryse Wouters, Veerle Derudder, Ivo Bolsens, Paul Six, Hugo De Man
Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks. Synthesis for Control Dominated Circuits (1992)
Daniel Gajski, Nikil D. Dutt
Benchmarking and the Art of Syntesis Tool Comparison. Synthesis for Control Dominated Circuits (1992)
A. J. W. M. ten Berg
Floorplan Optimized Topological Partitioning of Programmed Logic Arrays. Synthesis for Control Dominated Circuits (1992)
Jörg Biesenack, Norbert Wehn, A. Stoll, Michael Payer
Data Part Optimizations in the CALLAS Synthesis Environment. Synthesis for Control Dominated Circuits (1992)
J. F. M. Theeuwen, H. M. A. M. Arts, Jos T. J. van Eijndhoven, H. J. H. Sleuters, J. H. P. Wijdeven
Module Generation in an Architectural Synthesis Environment. Synthesis for Control Dominated Circuits (1992)
Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura
Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits (1992)
James Pardey
The Synthesis of a Parallel Controller from a Petri Net Model. Synthesis for Control Dominated Circuits (1992)
Antonio Martinez
Timing Model Accuracy Issues and Automated Library Characterization. Synthesis for Control Dominated Circuits (1992)
Steve C.-Y. Huang, Wayne H. Wolf
Timing-Driven State Assignment for Controller-Datapath Systems. Synthesis for Control Dominated Circuits (1992)
Régis Leveugle, C. Safina
Generation of optimized datapaths: bit-slice versus standard cells. Synthesis for Control Dominated Circuits (1992)
Inhag Park, Kevin O'Brien, Ahmed Amine Jerraya
AMICAL: Architectural Synthesis based on VHDL. Synthesis for Control Dominated Circuits (1992)
Andreas Münzner
BADGE - A synthesis tool for customized arithmetic building blocks. Synthesis for Control Dominated Circuits (1992)
H. Belhadj, Laurent Gerbaux, Marie-Claude Bertrand, Gabriele Saucier
Specification and Synthesis of Communicating Finite State Machines. Synthesis for Control Dominated Circuits (1992)
ChiLai Huang, Joseph Lis, Michael Quayle, Saurin Shroff
RTL Controller Synthesis. Synthesis for Control Dominated Circuits (1992)
Yang Wu, Ian Dorrington
RTL OptimizA: From Control Data Flow Graph to Logic Circuit. Synthesis for Control Dominated Circuits (1992)
Lotfi Ben Ammar, Alain Greiner
FITPATH: A Process-Independent Datapath Compiler Providing High Density Layout. Synthesis for Control Dominated Circuits (1992)
Laurent Gerbaux, Régis Leveugle, Gabriele Saucier
Synthesis of large controllers using ROM or PLA generators. Synthesis for Control Dominated Circuits (1992)
Peter Marwedel
Implementations of IF-statements in the TODOS microarchitecture synthesis system. Synthesis for Control Dominated Circuits (1992)
A. G. Jost, L. F. Wang, S. Periyalwar, William Robertson
Automatic Layout Synthesis of Pipelined Multipliers for Systolic Arrays. Synthesis for Control Dominated Circuits (1992)
Alan J. Coppola, Marek A. Perkowski, Robert Anderson, Jeffrey S. Freedman, Edmund Pierzchala
Tokenized State Machine Model for Synthesis of Sequential Circuits into EPLDs and FPGAs. Synthesis for Control Dominated Circuits (1992)
Francesco Curatelli, Daniele D. Caviglia, Marco Chirico, Giacomo M. Bisio
Optimization strategies in symbolic compaction. Synthesis for Control Dominated Circuits (1992)
Amnon Baron Cohen, Michael Shechory
Pathway: A datapath layout assembler. Synthesis for Control Dominated Circuits (1992)
Anne Mignotte, Marie-Claude Bertrand, Michel Crastes de Paulet, Jérôme Rampon, Gabriele Saucier
ASYL: A Control Driven RTL Synthesis System using Library Blocks. Synthesis for Control Dominated Circuits (1992)
Pierre Abouzeid, Régis Leveugle, Gabriele Saucier
Logic Synthesis for Automatic Layout. Synthesis for Control Dominated Circuits (1992)
Farhad Mavaddat
Data-Path Synthesis as Grammar Inference. Synthesis for Control Dominated Circuits (1992)
B. Conq, R. Etienne, T. Perez-Segovia
Design Library Portability: A Case Study. Synthesis for Control Dominated Circuits (1992)
Augusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man
Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers. Synthesis for Control Dominated Circuits (1992)