Pavlos M. Mattheakis

Publication Activity (10 Years)

Years Active: 2006-2020
Publications (10 Years): 7

Top Topics

Exponential Size

Highly Parallel

Adaptive Resonance Theory

Top Venues

ACM Great Lakes Symposium on VLSI

ACM Trans. Archit. Code Optim.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Dimitrios Mangiras, Pavlos M. Mattheakis, Pierre-Olivier Ribet, Giorgos Dimitrakopoulos
Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV. ISPD (2020)
Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery
Timing-Driven and Placement-Aware Multibit Register Composition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (8) (2019)
Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. DAC (2017)
Nikolaos Tampouratzis, Pavlos M. Mattheakis, Ioannis Papaefstathiou
Accelerating Intercommunication in Highly Parallel Systems. ACM Trans. Archit. Code Optim. 13 (4) (2016)
Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos
A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors. ACM Great Lakes Symposium on VLSI (2016)
Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet
Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. ACM Great Lakes Symposium on VLSI (2015)
Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan
Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (4) (2015)
Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan
Clock tree resynthesis for multi-corner multi-mode timing closure. ISPD (2014)
Giorgos Dimitrakopoulos, I. Seitanidis, Anastasios Psarras, K. Tsiouris, Pavlos M. Mattheakis, Jordi Cortadella
Hardware primitives for the synthesis of multithreaded elastic systems. DATE (2014)
Pavlos M. Mattheakis, Ioannis Papaefstathiou
Significantly reducing MPI intercommunication latency and power overhead in both embedded and HPC systems. ACM Trans. Archit. Code Optim. 9 (4) (2013)
Pavlos M. Mattheakis, Christos P. Sotiriou
Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition. VLSI Design (2013)
Pavlos M. Mattheakis, Christos P. Sotiriou, Peter A. Beerel
A polynomial time flow for implementing free-choice Petri-nets. ICCD (2012)
Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed. FPL (2006)