A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors.
Anastasios PsarrasJunghee LeePavlos M. MattheakisChrysostomos NicopoulosGiorgos DimitrakopoulosPublished in: ACM Great Lakes Symposium on VLSI (2016)
Keyphrases
- low power
- network on chip
- power dissipation
- cmos technology
- signal processor
- power consumption
- multi processor
- low cost
- high speed
- single chip
- nm technology
- parallel processing
- power reduction
- digital signal processing
- single processor
- mixed signal
- network simulator
- routing algorithm
- parallel algorithm
- low power consumption
- multi core processors
- energy efficiency
- cmos image sensor
- image sensor
- shared memory