Stefano Di Matteo

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 15

Top Topics

Integrity Checking

Fpga Implementation

Heterogeneous Platforms

Top Venues

Comput. Electr. Eng.

Publications

Pericle Perazzo, Stefano Di Matteo, Gianluca Dini, Sergio Saponara
On hardware acceleration of quantum-resistant FOTA systems in automotive. Comput. Electr. Eng. 118 (2024)
Stefano Di Matteo, Ivan Sarno, Sergio Saponara
CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms. IEEE Access 12 (2024)
Vasileios Tenentes, Stefano Di Matteo, Christos Zonios, Daniele Rossi, Sergio Saponara
RTL Flow for the Power Side-Channel Resilience Assessment of a Post-Quantum SHA-3 Accelerator. MOCAST (2024)
Daniele Rossi, Nicasio Canino, Stefano Di Matteo, Sergio Saponara, Vasileios Tenentes
Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures. SEEDA-CECNSM (2023)
Pietro Nannipieri, Stefano Di Matteo, Luca Crocetti, Luca Zulberti, Luca Fanucci, Sergio Saponara
Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative. ApplePies (2023)
Federico Pacini, Stefano Di Matteo, Pierpaolo Dini, Luca Fanucci, Francesco Bucchi
Innovative Plug-and-Play System for Electrification of Wheel-Chairs. IEEE Access 11 (2023)
Stefano Di Matteo, Matteo Lo Gerfo, Sergio Saponara
VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library. IEEE Access 11 (2023)
Stefano Di Matteo, Luca Zulberti, Federico Cosimo Lapenna, Pietro Nannipieri, Luca Crocetti, Luca Fanucci, Sergio Saponara
A PUF-Based Secure Boot for RISC-V Architectures. ApplePies (2023)
Pietro Nannipieri, Stefano Di Matteo, Luca Baldanzi, Luca Crocetti, Luca Zulberti, Sergio Saponara, Luca Fanucci
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative. IEEE Trans. Very Large Scale Integr. Syst. 30 (2) (2022)
Stefano Di Matteo, Sergio Saponara, Riccardo Locatelli
Design and Implementation on FPGA of a HW Accelerator for Post-Quantum RLWE Polynomial Operations. ApplePies (2022)
Luca Crocetti, Stefano Di Matteo, Pietro Nannipieri, Luca Fanucci, Sergio Saponara
Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source. Entropy 24 (2) (2022)
Pietro Nannipieri, Matteo Bertolucci, Luca Baldanzi, Luca Crocetti, Stefano Di Matteo, Francesco Falaschi, Luca Fanucci, Sergio Saponara
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative. Microprocess. Microsystems 87 (2021)
Pietro Nannipieri, Luca Baldanzi, Luca Crocetti, Stefano Di Matteo, Francesco Falaschi, Luca Fanucci, Sergio Saponara
CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes. ApplePies (2021)
Pietro Nannipieri, Stefano Di Matteo, Luca Zulberti, Francesco Albicocchi, Sergio Saponara, Luca Fanucci
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms. IEEE Access 9 (2021)
Luca Baldanzi, Luca Crocetti, Stefano Di Matteo, Luca Fanucci, Sergio Saponara, Patrice Hameau
Crypto Accelerators for Power-Efficient and Real-Time on-Chip Implementation of Secure Algorithms. ICECS (2019)