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SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative.

Pietro NannipieriMatteo BertolucciLuca BaldanziLuca CrocettiStefano Di MatteoFrancesco FalaschiLuca FanucciSergio Saponara
Published in: Microprocess. Microsystems (2021)
Keyphrases
  • design process
  • high speed
  • single chip
  • low cost
  • engineering design
  • functional verification
  • nm technology
  • image processing
  • case study
  • efficient implementation
  • low power
  • computer architecture