Pietro Nannipieri

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 25

Top Topics

Random Number Generator

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Pietro Nannipieri, Giacomo Bartolacci, Matteo Bertolucci, Luca Fanucci
Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload. IEEE Access 12 (2024)
Pietro Nannipieri, Stefano Di Matteo, Luca Crocetti, Luca Zulberti, Luca Fanucci, Sergio Saponara
Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative. ApplePies (2023)
Giovanni Quintarelli, Matteo Bertolucci, Pietro Nannipieri
Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry. IEEE Access 11 (2023)
Roberto Ciardi, Simone Vagaggini, Antonino Marino, Pietro Nannipieri, Luca Fanucci
SpaceART SpaceWire Sniffer for Link Monitoring: A Complete Communication Analysis in a Time-Constrained Test Scenario. Sensors 23 (3) (2023)
Matteo Monopoli, Luca Zulberti, Giovanni Todaro, Pietro Nannipieri, Luca Fanucci
Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip. PRIME (2023)
Stefano Di Matteo, Luca Zulberti, Federico Cosimo Lapenna, Pietro Nannipieri, Luca Crocetti, Luca Fanucci, Sergio Saponara
A PUF-Based Secure Boot for RISC-V Architectures. ApplePies (2023)
Pietro Nannipieri, Stefano Di Matteo, Luca Baldanzi, Luca Crocetti, Luca Zulberti, Sergio Saponara, Luca Fanucci
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative. IEEE Trans. Very Large Scale Integr. Syst. 30 (2) (2022)
Luca Crocetti, Stefano Di Matteo, Pietro Nannipieri, Luca Fanucci, Sergio Saponara
Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source. Entropy 24 (2) (2022)
Luca Zulberti, Matteo Monopoli, Pietro Nannipieri, Luca Fanucci
Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators. PRIME (2022)
Luca Zulberti, Pietro Nannipieri, Luca Fanucci
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture. DTIS (2021)
Pietro Nannipieri, Matteo Bertolucci, Luca Baldanzi, Luca Crocetti, Stefano Di Matteo, Francesco Falaschi, Luca Fanucci, Sergio Saponara
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative. Microprocess. Microsystems 87 (2021)
Pietro Nannipieri, Luca Baldanzi, Luca Crocetti, Stefano Di Matteo, Francesco Falaschi, Luca Fanucci, Sergio Saponara
CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes. ApplePies (2021)
Pietro Nannipieri, Stefano Di Matteo, Luca Zulberti, Francesco Albicocchi, Sergio Saponara, Luca Fanucci
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms. IEEE Access 9 (2021)
Pietro Nannipieri, Gianmarco Dinelli, Luca Fanucci
A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2019)
Pietro Nannipieri, Daniele Davalle, Stefano Nencioni, Paolo Lombardi, Luca Fanucci
Clustering Algorithm for a Spaceborne Lightning Imager: Design, Trade-Off, and FPGA Implementation. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 12 (8) (2019)
Gianmarco Dinelli, Gabriele Meoni, Pietro Nannipieri, Luca Dello Sterpaio, Antonino Marino, Luca Fanucci
Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus. ApplePies (2019)
Luca Dello Sterpaio, Antonino Marino, Pietro Nannipieri, Gianmarco Dinelli, Daniele Davalle, Luca Fanucci
A Complete EGSE Solution for the SpaceWire and SpaceFibre Protocol Based on the PXI Industry Standard. Sensors 19 (22) (2019)
Pietro Nannipieri, Gianmarco Dinelli, Luca Dello Sterpaio, Antonino Marino, Luca Fanucci
Design of a SpaceFibre High-Speed Satellite Interface ASIC. ApplePies (2019)
Luca Dello Sterpaio, Antonino Marino, Pietro Nannipieri, Gianmarco Dinelli, Luca Fanucci
AXI4LV: Design and Implementation of a Full-Speed AMBA AXI4-Burst DMA Interface for LabVIEW FPGA. ApplePies (2019)
Alessandro Leoni, Pietro Nannipieri, Luca Fanucci
VHDL Design of a SpaceFibre Routing Switch. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2019)
Luca Dello Sterpaio, Antonino Marino, Pietro Nannipieri, Luca Fanucci
Exploiting LabViewFpga Socketed CLIP to Design and Implement Soft-Core Based Complex Digital Architectures on PXI FPGA Target Boards. SMACD (2019)
Pietro Nannipieri, Luca Dello Sterpaio, Antonino Marino, Luca Fanucci
A PXI Based Implementation of a TLK2711 Equivalent Interface. ApplePies (2018)
Pietro Nannipieri, Gianmarco Dinelli, Daniele Davalle, Luca Fanucci
A SpaceFibre multi lane codec System on a Chip: enabling technology for low cost satellite EGSE. PRIME (2018)
Pietro Nannipieri, Daniele Davalle, Luca Fanucci
A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Pietro Nannipieri, Martina Anichini, Lorenzo Barsocchi, Giulia Becatti, Luca Buoni, Andrea Catarsi, Federico Celi, Paolo Di Giorgio, Paolo Fattibene, Eugenio Ferrato, Pietro Guardati, Edoardo Mancini, Gabriele Meoni, Federico Nesti, Stefano Piaquadio, Edoardo Pratelli, Lorenzo Quadrelli, Alessandro Simone Viglione, Francesco Zanaboni, Carlo Bartoli, Paolo Di Marco, Salvo Marcuccio, Roberto Di Rienzo, Luca Fanucci, Federico Baronti, Mauro Mameli, Sauro Filippeschi
The U-PHOS experience within the ESA student REXUS/BEXUS programme: A real space hands-on opportunity. EDUCON (2017)