Yiorgos Tsiatouhas

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 26

Top Topics

Defect Detection

Top Venues

IEEE Trans. Computers

Publications

Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas
Deep Learning Based Detection of Anti-Reflective Obstacles in VLC Systems. ICAIIC (2024)
Spyridon Spyridonos, Yiorgos Tsiatouhas
Testing Algorithms for Hard to Detect Thermal Crosstalk Induced Write Disturb Faults in Phase Change Memories. DATE (2024)
Vasileios Tenentes, Athanasios Xynos, Christos Zonios, Asimina Koutra, Christina Dilopoulou, Konstantinos Tsampiras, Yiorgos Tsiatouhas, Daniele Rossi
Embedded Platforms for Trusted Edge Computing Towards Quality Assurance Along the Supply Chain. SEEDA-CECNSM (2023)
Athanasios Xynos, Vasileios Tenentes, Yiorgos Tsiatouhas
SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs. ETS (2023)
Helen-Maria Dounavi, Yiorgos Tsiatouhas
An aging monitoring scheme for SRAM decoders. Integr. 88 (2023)
Christina Dilopoulou, Yiorgos Tsiatouhas
BTI Aging Influence in SRAM-based In-Memory Computing Schemes and its Mitigation. ICECS (2023)
Christina Dilopoulou, Yiorgos Tsiatouhas
BTI Aging Influence and Mitigation in Neural Networks Oriented In-Memory Computing SRAMs. MOCAST (2023)
Christoforos Papaioannou, Marina E. Plissiti, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas
Signal decoding in an NLOS VLC system with the presence of anti-reflective obstacles. BlackSeaCom (2022)
Constantinos Efstathiou, Laura Agalioti, Yiorgos Tsiatouhas
Efficient Dynamic Logic Magnitude Comparators. VLSI-SoC (2022)
Spyridon Spyridonos, Yiorgos Tsiatouhas
BTI Aging Influence on Charge Pump Circuits. MOCAST (2022)
Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas
An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems. MeditCom (2021)
Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos
A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs. J. Electron. Test. 37 (2) (2021)
Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas
Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier. J. Electron. Test. 37 (1) (2021)
Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos
An Alternative Post-bond Testing Method for TSVs. MOCAST (2020)
Helen-Maria Dounavi, Yiorgos Tsiatouhas
Monitoring of BTI and HCI Aging in SRAM Decoders. ETS (2020)
Costas Efstathiou, Yiorgos Tsiatouhas
On the Static CMOS Implementation of Magnitude Comparators. PATMOS (2019)
Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas
Periodic Aging Monitoring in SRAM Sense Amplifiers. IOLTS (2018)
Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas
Aging monitoring in SRAM sense amplifiers. MOCAST (2018)
Yiorgos Tsiatouhas
Periodic Bias-Temperature Instability monitoring in SRAM cells. ETS (2017)
Yiorgos Sfikas, Yiorgos Tsiatouhas
Variation tolerant BTI monitoring in SRAM cells. IOLTS (2017)
Stylianos-Georgios Papadopoulos, Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos
Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVs. PATMOS (2017)
Yiorgos Sfikas, Yiorgos Tsiatouhas
BTI and HCI degradation detection in SRAM cells. MOCAST (2017)
Raghava Katreepalli, Hemanth Chemanchula, Themistoklis Haniotakis, Yiorgos Tsiatouhas
Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design. ISVLSI (2016)
Yiorgos Sfikas, Yiorgos Tsiatouhas
Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs. IEEE Trans. Computers 65 (7) (2016)
Stefanos Valadimas, Angela Arapoyanni, Yiorgos Tsiatouhas
Timing error mitigation in microprocessor cores. ICECS (2016)
Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni
Timing Error Tolerance in Small Core Designs for SoC Applications. IEEE Trans. Computers 65 (2) (2016)
Helen-Maria Dounavi, Yiorgos Tsiatouhas, Angela Arapoyanni
Scan chain based at-speed diagnosis in the presence of scan output compaction schemes. Panhellenic Conference on Informatics (2015)
Katerina Katsarou, Yiorgos Tsiatouhas
Soft error immune latch under SEU related double-node charge collection. IOLTS (2015)
Anthi Anastasiou, Yiorgos Tsiatouhas, Angela Arapoyanni
On the reuse of existing error tolerance circuitry for low power scan testing. ISCAS (2015)
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
testing in digital integrated circuits. Integr. 50 (2015)
John Liaperdos, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Yiorgos Tsiatouhas, Angela Arapoyanni, Xin Li
Fast deployment of alternate analog test using Bayesian model fusion. DATE (2015)
Yiorgos Sfikas, Yiorgos Tsiatouhas, Mottaqiallah Taouil, Said Hamdioui
On resistive open defect detection in DRAMs: The charge accumulation effect. ETS (2015)
John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas
A method for the estimation of defect detection probability of analog/RF defect-oriented tests. DATE (2015)
Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas
Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches. IEEE Trans. Very Large Scale Integr. Syst. 22 (1) (2014)
Helen-Maria Dounavi, Yiorgos Tsiatouhas
Stuck-at fault diagnosis in scan chains. DTIS (2014)
Ran Wang, Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty
Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (8) (2014)
Katerina Katsarou, Yiorgos Tsiatouhas
Double node charge sharing SEU tolerant latch design. IOLTS (2014)
Yiorgos Sfikas, Yiorgos Tsiatouhas, Said Hamdioui
Layout-Based Refined NPSF Model for DRAM Characterization and Testing. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Stefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos
The Time Dilation Technique for Timing Error Tolerance. IEEE Trans. Computers 63 (5) (2014)
Anthi Anastasiou, Yiorgos Tsiatouhas
Power efficient scan testing by exploiting existing error tolerance circuitry in a design. ETS (2014)
Efi Arvaniti, Yiorgos Tsiatouhas
Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique. J. Electron. Test. 30 (3) (2014)
Katerina Katsarou, Yiorgos Tsiatouhas, Angela Arapoyanni
NBTI aging tolerance in pipeline based designs NBTI. IOLTS (2013)
Costas Efstathiou, Zaher Owda, Yiorgos Tsiatouhas
New High-Speed Multioutput Carry Look-Ahead Adders. IEEE Trans. Circuits Syst. II Express Briefs (10) (2013)
Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Petros Xarchakos
Effective Timing Error Tolerance in Flip-Flop Based Core Designs. J. Electron. Test. 29 (6) (2013)
John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas
A Built-In Voltage Measurement Technique for the Calibration of RF Mixers. IEEE Trans. Instrum. Meas. 62 (4) (2013)
Maria Chalkia, Yiorgos Tsiatouhas
The leafs scan-chain for test application time and scan power reduction. ICECS (2012)
Lampros Dermentzoglou, John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas
Testing wireless transceivers' RF front-ends utilizing defect-oriented BIST techniques. ICECS (2012)
Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Adrian Evans
Single event upset tolerance in flip-flop based microprocessor cores. DFT (2012)
Efi Arvaniti, Yiorgos Tsiatouhas
Low power scan by partitioning and scan hold. DDECS (2012)
Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni
Cost and power efficient timing error tolerance in flip-flop based microprocessor cores. ETS (2012)
Ioannis Voyiatzis, Costas Efstathiou, Yiorgos Tsiatouhas, Cleo Sgouropoulou
A novel architecture to reduce test time in march-based SRAM tests. DTIS (2012)
Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty
Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches. ETS (2011)
Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty
A BIST scheme for testing and repair of multi-mode power switches. IOLTS (2011)
Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas
A Robust and Reconfigurable Multi-mode Power Gating Architecture. VLSI Design (2011)
Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni
Timing error tolerance in nanometer ICs. IOLTS (2010)
Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas
A Build-In Self-Test technique for RF Mixers. DDECS (2010)
Themistoklis Haniotakis, Zaher Owda, Yiorgos Tsiatouhas
Memory-Less Pipeline Dynamic Circuit Design Technique. ISVLSI (2010)
Yiannis Moisiadis, Yiorgos Tsiatouhas
A Receiver Circuit for Low-Swing Interconnect Schemes. ISVLSI (2010)
Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas
A Built-In-Test Circuit for RF Differential Low Noise Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Yiorgos Sfikas, Yiorgos Tsiatouhas
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing. DDECS (2009)
Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
A Current Mode, Parallel, Two-Rail Code Checker. IEEE Trans. Computers 57 (8) (2008)
Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos
Timing Error Detection and Correction by Time Dilation. VLSI-SoC (Selected Papers) (2008)
Yiorgos Tsiatouhas, Angela Arapoyanni, Dionisis Skias
A Scan Flip-Flop for Low-Power Scan Operation. ICECS (2007)
Lampros Dermentzoglou, Anastasios Karagounis, Aggeliki Arapoyanni, Yiorgos Tsiatouhas
An Embedded Test Circuit for RF Single Ended Low Noise Amplifiers. ICECS (2007)
Yiorgos Tsiatouhas
A Stress-Relaxed Negative Voltage-Level Converter. IEEE Trans. Circuits Syst. II Express Briefs (3) (2007)
Konstantinos Limniotis, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
A Design Technique for Energy Reduction in NORA CMOS Logic. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2006)
Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism. ICECS (2006)
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
An embedded IDDQ testing circuit and technique. ICECS (2005)
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir
testing circuit. ESSCIRC (2005)
Yiorgos Tsiatouhas, Konstantinos Limniotis, Angela Arapoyanni, Themistoklis Haniotakis
A low power NORA circuit design technique based on charge recycling. ICECS (2003)
Lampros Dermentzoglou, Yiorgos Tsiatouhas, Angela Arapoyanni
A novel scheme for testing radio frequency voltage controlled oscillators. ICECS (2003)