Costas Efstathiou

Publication Activity (10 Years)

Years Active: 1984-2019
Publications (10 Years): 6

Top Topics

Data Compression

Hough Transform

Top Venues

Panhellenic Conference on Informatics

Comput. Electr. Eng.

Publications

Costas Efstathiou, Yiorgos Tsiatouhas
On the Static CMOS Implementation of Magnitude Comparators. PATMOS (2019)
Ioannis Voyiatzis, Costas Efstathiou
SIC pair generation in near-optimal time with carry-look ahead adders. DTIS (2018)
Costas Efstathiou, K. Dimolikas, C. Papaioannou, Y. Tsiatouhas
Low Power and High Speed Static CMOS Digital Magnitude Comparators. ICECS (2018)
Ioannis Voyiatzis, Costas Efstathiou
On the generation of binary functions with low-overhead. DTIS (2017)
Ioannis Voyiatzis, Costas Efstathiou, Kiriakos Patriarcheas
Software-based SIC pair Generation. PCI (2016)
Ioannis Voyiatzis, Costas Efstathiou
Low Cost Boolean Function generation. PCI (2016)
Ioannis Voyiatzis, Costas Efstathiou
Accumulator-based generation for serial TPG. Panhellenic Conference on Informatics (2015)
Ioannis Voyiatzis, Dimitris J. Kavvadias, S. Sinitos, K. Vlahantonis, P. Kyrkos, Cleo Sgouropoulou, Costas Efstathiou
Test set embedding into hardware generated sequences using an embedding algorithm. DTIS (2015)
Ioannis Voyiatzis, Costas Efstathiou
On the use of hard faults to generate test sets. Panhellenic Conference on Informatics (2015)
Ioannis Voyiatzis, Cleo Sgouropoulou, Costas Efstathiou
A concurrent BIST scheme for read only memories. DTIS (2015)
Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
Low overhead output response compaction in RAS architectures. DTIS (2014)
Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs. DTIS (2014)
I. Nikopoulos, Athanasios Milidonis, Costas Efstathiou, Cleo Sgouropoulou, Ioannis Voyiatzis
Stealth Assessment of Hardware Trojans in simple Processors. Panhellenic Conference on Informatics (2014)
Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kiamal Z. Pekmestzi, Costas Efstathiou
High performance MAC designs. IDT (2014)
Ioannis Voyiatzis, Costas Efstathiou
Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells. IEEE Trans. Very Large Scale Integr. Syst. 22 (7) (2014)
Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
Transparent testing for intra-word memory faults. IDT (2013)
Ioannis Voyiatzis, Stelios Neophytou, Maria K. Michael, Stavros Hadjitheophanous, Cleo Sgouropoulou, Costas Efstathiou
Test set embedding into accumulator-generated sequences targeting hard-to-detect faults. IDT (2013)
Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
Embedding test vectors in accumulator - based TPG using progressive search. DTIS (2013)
Costas Efstathiou, Nikolaos Moschopoulos, Ioannis Voyiatzis, Kiamal Z. Pekmestzi
+ 1 dot product and generalized multiply-add units. Comput. Electr. Eng. 39 (2) (2013)
Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
Symmetric transparent online BIST for arrays of word-organized RAMs. DTIS (2013)
Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
A low-cost input vector monitoring concurrent BIST scheme. IOLTS (2013)
Costas Efstathiou, Zaher Owda, Yiorgos Tsiatouhas
New High-Speed Multioutput Carry Look-Ahead Adders. IEEE Trans. Circuits Syst. II Express Briefs (10) (2013)
Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou, Athanasios Milidonis
An effective two-pattern test generator for Arithmetic BIST. Comput. Electr. Eng. 39 (2) (2013)
Ioannis Voyiatzis, Costas Efstathiou, Said Hamdioui, Cleo Sgouropoulou
ALU based address generation for RAMs. DTIS (2012)
Ioannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou
Test vector embedding in accumulators with stored carry in O(1) time. DTIS (2012)
Ioannis Voyiatzis, Costas Efstathiou, Dimitris Magos, Cleo Sgouropoulou
Test set embedding into low-power sequences based on a traveling salesman problem formulation. DTIS (2012)
Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou, Athanasios Milidonis
Arithmetic module-based built-in self test architecture for two-pattern testing. IET Comput. Digit. Tech. 6 (4) (2012)
Ioannis Voyiatzis, Kyriakos Axiotis, Nikolaos S. Papaspyrou, Hera Antonopoulou, Costas Efstathiou
Test Set Embedding into Low-Power BIST Sequences Using Maximum Bipartite Matching. Panhellenic Conference on Informatics (2012)
Ioannis Voyiatzis, Costas Efstathiou, Yiorgos Tsiatouhas, Cleo Sgouropoulou
A novel architecture to reduce test time in march-based SRAM tests. DTIS (2012)
Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou
A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture. ETS (2011)
Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou
+1 multi-operand adders and residue generators. Integr. 43 (1) (2010)
Costas Efstathiou
+1 subtractors for weighted operands. ICECS (2010)
Dimitris J. Kavvadias, S. Sinitos, Ioannis Voyiatzis, Hera Antonopoulou, Costas Efstathiou
On Embedding Test Sets into Hardware Generated Sequences. Panhellenic Conference on Informatics (2010)
Ioannis Voyiatzis, Costas Efstathiou
An efficient architecture for accumulator-based test generation of SIC pairs. Microelectron. J. 41 (8) (2010)
Haridimos T. Vergos, Costas Efstathiou
+1 adder architectures. Integr. 42 (2) (2009)
Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou
+ 1 multi-operand adders. ICECS (2008)
Haridimos T. Vergos, Costas Efstathiou
Addition. IEEE Trans. Circuits Syst. II Express Briefs (10) (2008)
Haridimos T. Vergos, Costas Efstathiou
+1 multipliers. IET Comput. Digit. Tech. 1 (1) (2007)
Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15 (4) (2007)
Nicolas Sklavos, Costas Efstathiou
SecurID Authenticator: On the Hardware Implementation Efficiency. ICECS (2007)
Athanasios P. Kakarountas, Haralambos Michail, Costas E. Goutis, Costas Efstathiou
Implementation of HSSec: a high-speed cryptographic co-processor. ETFA (2007)
Haridimos T. Vergos, Costas Efstathiou
+ 1 Multipliers. DSD (2006)
Giorgos Dimitrakopoulos, D. G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
New architectures for modulo 2N - 1 adders. ICECS (2005)
Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers 54 (4) (2005)
Haridimos T. Vergos, Costas Efstathiou
On the Design of Efficient Modular Adders. J. Circuits Syst. Comput. 14 (5) (2005)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
-1 Multipliers. IEEE Trans. Computers 53 (3) (2004)
Haridimos T. Vergos, Costas Efstathiou
+ 1 Squarer Design. DSD (2004)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
Fast Parallel-Prefix Modulo 2^n+1 Adders. IEEE Trans. Computers 53 (9) (2004)
Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
+1 tree multipliers for diminished-1 operands. ICECS (2003)
D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
An Efficient BIST scheme for High-Speed Adders. IOLTS (2003)
K. Katzourakis, George Kormentzas, Kimon P. Kontovasilis, Costas Efstathiou
A Virtual Signalling Protocol for Transparently Embedding Advanced Traffic Control and Resource Management Functionality in ATM Core Networks. MMNS (2003)
Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP (2003)
Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
Deterministic BIST for RNS Adders. IEEE Trans. Computers 52 (7) (2003)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
Modulo 2n±1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers 52 (11) (2003)
D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
Efficient BIST schemes for RNS datapaths. ISCAS (5) (2003)
Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
- 1 adders. ISCAS (5) (2003)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
Ling adders in CMOS standard cell technologies. ICECS (2002)
Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos
+1 Adder Design. IEEE Trans. Computers 51 (12) (2002)
Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. LATW (2001)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
±1 adders. ICECS (2001)
Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou
Concurrent Detection of Soft Errors Based on Current Monitoring. IOLTW (2001)
Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic (2001)
Costas Efstathiou, Haridimos T. Vergos
-1 multipliers. ICECS (2000)
Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos
High-Speed Parallel-Prefix Modulo 2n-1 Adders. IEEE Trans. Computers 49 (7) (2000)
Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
On Testability of Multiple Precharged Domino Logic. ISQED (2000)
Antonis M. Paschalis, Costas Efstathiou, Constantine Halatsis
An Efficient TSC 1-out-of-3 Code Checker. IEEE Trans. Computers 39 (3) (1990)
Costas Efstathiou, Constantine Halatsis
Modular design of totally self-checking checkers for 1-out-of-n codes. Fehlertolerierende Rechensysteme (1984)