A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme.

Haridimos T. Vergos Dimitris Nikolos Maciej Bellos Costas Efstathiou

Published in: LATW (2001)

Keyphrases

test set
low power
power consumption
low cost
high speed
error rate
training set

single chip
cmos technology
power dissipation
wireless transmission
training data
test data
vlsi circuits

high power
evaluation methodology
mixed signal
low power consumption
power reduction
logic circuits
digital signal processing

gate array
learning algorithm
vlsi architecture
image sensor
decision trees
face detector
real time