Haridimos T. Vergos

Publication Activity (10 Years)

Years Active: 1995-2016
Publications (10 Years): 2

Top Topics

Robust Image Watermarking

Hamming Distance

Top Venues

Circuits Syst. Signal Process.

Publications

George Blanas, Haridimos T. Vergos
Extending the viability of power signature - Based IP watermarking in the SoC era. ICECS (2016)
Haridimos T. Vergos, Dimitris Bakalis, A. Anastasiou
Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators. Circuits Syst. Signal Process. 34 (4) (2015)
Anastasios N. Bikos, Haridimos T. Vergos
Easily verified IP watermarking. DTIS (2014)
Alexios Thanos, Haridimos T. Vergos
Fast parallel-prefix Ling-carry adders in QCA nanotechnology. ICECS (2013)
Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
Reverse converters for RNSs with diminished-one encoded channels. EUROCON (2013)
Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
RNS assisted image filtering and edge detection. DSP (2013)
Haridimos T. Vergos, Giorgos Dimitrakopoulos
On Modulo 2^n+1 Adder Design. IEEE Trans. Computers 61 (2) (2012)
Haridimos T. Vergos, Dimitris Bakalis
Area-time efficient multi-modulus adders and their applications. Microprocess. Microsystems 36 (5) (2012)
Haridimos T. Vergos
Area-time efficient end-around inverted carry adders. Integr. 45 (4) (2012)
Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
SUT-RNS Residue-to-Binary Converters Design. DSD (2012)
Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
±1 Subtractors and Adders/Subtractors. Circuits Syst. Signal Process. 30 (6) (2011)
Dimitris Bakalis, Haridimos T. Vergos, Anastasia Spyrou
±1 squarers. Integr. 44 (3) (2011)
Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion. DSD (2011)
Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
On the use of double-LSB and signed-LSB encodings for RNS. DSP (2011)
Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou
+1 multi-operand adders and residue generators. Integr. 43 (1) (2010)
Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
SUT-RNS Forward and Reverse Converters. ISVLSI (Selected papers) (2010)
Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
SUT-RNS Forward and Reverse Converters. ISVLSI (2010)
Dimitris Bakalis, Haridimos T. Vergos
Area-Efficient Multi-moduli Squarers for RNS. DSD (2010)
Haridimos T. Vergos, Dimitris Bakalis
+ 1 Arithmetic Components. J. Circuits Syst. Comput. 19 (5) (2010)
Haridimos T. Vergos
A Family of Area-Time Efficient Modulo 2n+1 Adders. ISVLSI (2010)
Haridimos T. Vergos, Costas Efstathiou
+1 adder architectures. Integr. 42 (2) (2009)
Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
Novel modulo 2n+1 subtractors. DPS (2009)
Anastasia Spyrou, Dimitris Bakalis, Haridimos T. Vergos
Efficient architectures for modulo 2n-1 squares. DPS (2009)
Haridimos T. Vergos, Dimitris Bakalis
On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. DSD (2008)
Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou
+ 1 multi-operand adders. ICECS (2008)
Haridimos T. Vergos, Costas Efstathiou
Addition. IEEE Trans. Circuits Syst. II Express Briefs (10) (2008)
Haridimos T. Vergos, Costas Efstathiou
+1 multipliers. IET Comput. Digit. Tech. 1 (1) (2007)
Haridimos T. Vergos
An Efficient BIST Scheme for Non-Restoring Array Dividers. DSD (2007)
D. Adamidis, Haridimos T. Vergos
RNS multiplication/sum-of-squares units. IET Comput. Digit. Tech. 1 (1) (2007)
Dimitris Bakalis, Kostas Adaos, D. Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos
A core generator for arithmetic cores and testing structures with a network interface. J. Syst. Archit. 52 (1) (2006)
Haridimos T. Vergos, Costas Efstathiou
+ 1 Multipliers. DSD (2006)
Giorgos Dimitrakopoulos, D. G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
New architectures for modulo 2N - 1 adders. ICECS (2005)
Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers 54 (4) (2005)
Haridimos T. Vergos, Costas Efstathiou
On the Design of Efficient Modular Adders. J. Circuits Syst. Comput. 14 (5) (2005)
Nikolaos Kostaras, Haridimos T. Vergos
KoVer: A Sophisticated Residue Arithmetic Core Generator. IEEE International Workshop on Rapid System Prototyping (2005)
D. Adamidis, Haridimos T. Vergos
- 1 multiplication/sum-of-squares units. ECCTD (2005)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
-1 Multipliers. IEEE Trans. Computers 53 (3) (2004)
Haridimos T. Vergos, Costas Efstathiou
+ 1 Squarer Design. DSD (2004)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
Fast Parallel-Prefix Modulo 2^n+1 Adders. IEEE Trans. Computers 53 (9) (2004)
Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
+1 tree multipliers for diminished-1 operands. ICECS (2003)
D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
An Efficient BIST scheme for High-Speed Adders. IOLTS (2003)
Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP (2003)
Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
Deterministic BIST for RNS Adders. IEEE Trans. Computers 52 (7) (2003)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
Modulo 2n±1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers 52 (11) (2003)
D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
Efficient BIST schemes for RNS datapaths. ISCAS (5) (2003)
Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
- 1 adders. ISCAS (5) (2003)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
Ling adders in CMOS standard cell technologies. ICECS (2002)
Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. J. Syst. Archit. 48 (4-5) (2002)
Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos
+1 Adder Design. IEEE Trans. Computers 51 (12) (2002)
Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou
Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. VLSI Design 2001 (3) (2001)
Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. LATW (2001)
Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
±1 adders. ICECS (2001)
Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic (2001)
Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos
On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ISQED (2001)
Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos
Low Power BIST for Wallace Tree-Based Fast Multipliers. ISQED (2000)
Costas Efstathiou, Haridimos T. Vergos
-1 multipliers. ICECS (2000)
Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos
High-Speed Parallel-Prefix Modulo 2n-1 Adders. IEEE Trans. Computers 49 (7) (2000)
Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. DATE (1999)
C. Ninos, Haridimos T. Vergos, Dimitris Nikolos
Design and Analysis of On-Chip CPU Pipelined Caches. VLSI (1999)
Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis
On Path Delay Fault Testing of Multiplexer - Based Shifters. Great Lakes Symposium on VLSI (1999)
Haridimos T. Vergos, Maciej Bellos, Dimitris Nikolos
Path delay fault testing of Benes multistage interconnection networks. ICECS (1999)
Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. EDCC (1999)
Dimitris Nikolos, Haridimos T. Vergos
On the Yield of VLSI Processors with On-Chip CPU Cache. IEEE Trans. Computers 48 (10) (1999)
Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. DFT (1999)
G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos
Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. Asian Test Symposium (1999)
Dimitris Nikolos, Haridimos T. Vergos, Antonis Vazaios, Spyros Voulgaris
Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches. DFT (1996)
Dimitris Nikolos, Haridimos T. Vergos
On the Yield of VLSI Processors with on-chip CPU Cache. EDCC (1996)
Haridimos T. Vergos, Dimitris Nikolos
Efficient fault tolerant cache memory design. Microprocess. Microprogramming 41 (2) (1995)