Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches.
Dimitris NikolosHaridimos T. VergosAntonis VazaiosSpyros VoulgarisPublished in: DFT (1996)
Keyphrases
- single chip
- vlsi design
- signal processor
- memory access
- processor array
- vlsi implementation
- high speed
- chip design
- signal processing
- multithreading
- low power
- parallel algorithm
- memory subsystem
- parallel processing
- parallel computing
- vlsi circuits
- low cost
- power dissipation
- data access
- main memory
- mixed signal
- physical design
- parallel computation
- processor core
- analog vlsi
- instruction set
- high density
- parallel implementation
- image processing
- circuit design
- mesh connected
- shared memory
- network load
- caching scheme
- cache misses
- distributed memory
- image sensor
- single processor