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On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation.
Dimitris Bakalis
Emmanouil Kalligeros
Dimitris Nikolos
Haridimos T. Vergos
George Alexiou
Published in:
J. Syst. Archit. (2002)
Keyphrases
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low power
single chip
power consumption
high speed
low cost
low power consumption
vlsi architecture
gate array
logic circuits
cmos technology
digital signal processing
mixed signal
power dissipation
power reduction
high power
vlsi circuits
b tree
wireless transmission
real time