Y. Tsiatouhas

Publication Activity (10 Years)

Years Active: 1998-2018
Publications (10 Years): 1

Top Topics

Statistically Significant

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Costas Efstathiou, K. Dimolikas, C. Papaioannou, Y. Tsiatouhas
Low Power and High Speed Static CMOS Digital Magnitude Comparators. ICECS (2018)
John Liaperdos, Angela Arapoyanni, Y. Tsiatouhas
Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (9) (2013)
Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15 (4) (2007)
Y. Tsiatouhas, Angela Arapoyanni
High fan-in differential current mirror logic. ISCAS (2006)
Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou
Fast, Parallel Two-Rail Code Checker with Enhanced Testability. IOLTS (2005)
Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni
A Built-In Self-Test Scheme for Differential Ring Oscillators. ISQED (2005)
A. Rao, Th. Haniotakis, Y. Tsiatouhas, H. Djemil
The Use of Pre-Evaluation Phase in Dynamic CMOS Logic. ISVLSI (2005)
Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . ISVLSI (2004)
Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs. J. Electron. Test. 20 (5) (2004)
Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators. J. Electron. Test. 20 (2) (2004)
A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky
A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. IOLTS (2004)
Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
An Embedded IDDQ Testing Architecture and Technique. ISQED (2003)
Y. Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Th. Haniotakis
A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs. IOLTS (2003)
Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
A new technique for IDDQ testing in nanometer technologies. Integr. 31 (2) (2002)
Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. IOLTW (2002)
A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology. ISCAS (5) (2002)
Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
Extending the Viability of IDDQ Testing in the Deep Submicron Era. ISQED (2002)
A. Chrisanthopoulos, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni
New test pattern generation units for NPSF oriented memory built-in self test. ICECS (2001)
Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou
Concurrent Detection of Soft Errors Based on Current Monitoring. IOLTW (2001)
A. Chrisanthopoulos, Yiannis Moisiadis, A. Varagis, Y. Tsiatouhas, Angela Arapoyanni
A new flash memory sense amplifier in 0.18 μm CMOS technology. ICECS (2001)
Y. Tsiatouhas, A. Chrisanthopoulos, George Kamoulakos, Th. Haniotakis
New memory sense amplifier designs in CMOS technology. ICECS (2000)
Dionisis Skias, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni
A state assignment algorithm for finite state machines. ICECS (2000)
George Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni
Management of charge pump circuits. Integr. 30 (1) (2000)
A. Chrisanthopoulos, George Kamoulakos, Y. Tsiatouhas, Angela Arapoyanni
A test pattern generation unit for memory NPSF built-in self test. ICECS (2000)
Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos
A Compact Built-In Current Sensor for IDDQ Testing. IOLTW (2000)
Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos
A Versatile Built-In Self-Test Scheme for Delay Fault Testing. DATE (2000)
Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
On Testability of Multiple Precharged Domino Logic. ISQED (2000)
Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. DATE (1999)
Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis
On Path Delay Fault Testing of Multiplexer - Based Shifters. Great Lakes Symposium on VLSI (1999)
Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni
Novel domino logic designs. ICECS (1999)
Y. Tsiatouhas, Th. Haniotakis
A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. DFT (1999)
Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas
C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. DFT (1998)