Themistoklis Haniotakis

Publication Activity (10 Years)

Years Active: 2002-2020
Publications (10 Years): 17

Top Topics

Threshold Values

Top Venues

Publications

Konstantinos Poulos, Themistoklis Haniotakis
A Built In Test circuit for waveform classification at high frequencies. NATW (2020)
Konstantinos Poulos, Iraklis Anagnostopoulos, Themistoklis Haniotakis
ARIAN: A Scalable Method for Adding aRbItrAry Numbers on Modern Processors. ISCAS (2020)
Theodoros Simopoulos, George Alexiou, Themistoklis Haniotakis
Implementation Guidelines of WDSRAM and Comparison with Typical SRAM Using Nanoscale Hierarchical Implementation Model. J. Circuits Syst. Comput. 28 (Supplement-1) (2019)
Raghava Katreepalli, Themistoklis Haniotakis
Power efficient synchronous counter design. Comput. Electr. Eng. 75 (2019)
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2018)
Theodoros Simopoulos, Themistoklis Haniotakis, George Alexiou
A 1Kx32 bit WDSRAM page with rapid write access. DTIS (2018)
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
A new method to identify threshold logic functions. DATE (2017)
Raghava Katreepalli, Themistoklis Haniotakis
High Speed Power Efficient Carry Select Adder Design. ISVLSI (2017)
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
More Efficient Testing of Metal-Oxide Memristor-Based Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (6) (2017)
Konstantinos Poulos, Jayasurya Kuchi, Themistoklis Haniotakis
An enhanced approach to reduce test application time through limited shift operations in scan chains. NATW (2017)
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
Reducing power, area, and delay of threshold logic gates considering non-integer weights. ISCAS (2017)
Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas
Delay Analysis for Current Mode Threshold Logic Gate Designs. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Raghava Katreepalli, Hemanth Chemanchula, Themistoklis Haniotakis, Yiorgos Tsiatouhas
Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design. ISVLSI (2016)
Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis
ATPG for Delay Defects in Current Mode Threshold Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (11) (2016)
Wisam Aljubouri, Spyros Tragoudas, Themistoklis Haniotakis
Identification of delay defects on embedded paths using one current sensor. DTIS (2016)
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
Fast march tests for defects in resistive memory. NANOARCH (2015)
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
testing in digital integrated circuits. Integr. 50 (2015)
Theodoros Simopoulos, Themistoklis Haniotakis, George Alexiou
Implementation of a Low Leakage Standard Cell Library based on materials from UMC 65nm technology. Panhellenic Conference on Informatics (2014)
Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis
ATPG for transition faults of pipelined threshold logic circuits. DTIS (2014)
Wisam Aljubouri, Ahish Mysore Somashekar, Themistoklis Haniotakis, Spyros Tragoudas
Diagnosis of segment delay defects with current sensing. DFT (2014)
Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas
Low power and high speed current-mode memristor-based TLGs. DFTS (2013)
Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas
Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission. Ad Hoc Networks 10 (3) (2012)
Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas
Delay Analysis for an N-Input Current Mode Threshold Logic Gate. ISVLSI (2012)
Chandra Babu Dara, Spyros Tragoudas, Themistoklis Haniotakis
A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate. DFT (2011)
Michael N. Skoufis, Kedar Karmarkar, Spyros Tragoudas, Themistoklis Haniotakis
A Data Capturing Method for Buses on Chip. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Themistoklis Haniotakis, Zaher Owda, Yiorgos Tsiatouhas
Memory-Less Pipeline Dynamic Circuit Design Technique. ISVLSI (2010)
Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
A Current Mode, Parallel, Two-Rail Code Checker. IEEE Trans. Computers 57 (8) (2008)
Michael N. Skoufis, Kedar Karmarkar, Themistoklis Haniotakis, Spyros Tragoudas
A High-Performance Bus Architecture for Strongly Coupled Interconnects. ISQED (2008)
Dimitrios Kagaris, Themistoklis Haniotakis
A Methodology for Transistor-Efficient Supergate Design. IEEE Trans. Very Large Scale Integr. Syst. 15 (4) (2007)
Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15 (4) (2007)
Dimitri Kagaris, Themistoklis Haniotakis
Transistor-Level Synthesis for Low-Power Applications. ISQED (2007)
Michael N. Skoufis, Haibo Wang, Themistoklis Haniotakis, Spyros Tragoudas
Glitch Control with Dynamic Receiver Threshold Adjustment. ISQED (2007)
Konstantinos Limniotis, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni
A Design Technique for Energy Reduction in NORA CMOS Logic. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2006)
Dimitri Kagaris, Themistoklis Haniotakis
Transistor-Level Optimization of Supergates. ISQED (2006)
Edward Flanigan, Themistoklis Haniotakis, Spyros Tragoudas
An Improved Method for Identifying Linear Dependencies in Path Delay Faults. ISQED (2006)
Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism. ICECS (2006)
Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou
Fast, Parallel Two-Rail Code Checker with Enhanced Testability. IOLTS (2005)
Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
An embedded IDDQ testing circuit and technique. ICECS (2005)
Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas
A security protocol for sensor networks. GLOBECOM (2005)
Themistoklis Haniotakis, Spyros Tragoudas, G. Pani
Reduced Test Application Time Based on Reachability Analysis. ISQED (2005)
Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas
Design and Evaluation of a Security Scheme for Sensor Networks. ISQED (2005)
Maria K. Michael, Themistoklis Haniotakis, Spyros Tragoudas
A unified framework for generating all propagation functions for logic errors and events. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (6) (2004)
Themistoklis Haniotakis, Spyros Tragoudas, Constantinos Kalapodas
Security enhancement through multiple path transmission in ad hoc networks. ICC (2004)
Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs. J. Electron. Test. 20 (5) (2004)
Yiorgos Tsiatouhas, Konstantinos Limniotis, Angela Arapoyanni, Themistoklis Haniotakis
A low power NORA circuit design technique based on charge recycling. ICECS (2003)
A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis
SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology. ISCAS (5) (2002)