Test Set Embedding into Low-Power BIST Sequences Using Maximum Bipartite Matching.
Ioannis VoyiatzisKyriakos AxiotisNikolaos S. PapaspyrouHera AntonopoulouCostas EfstathiouPublished in: Panhellenic Conference on Informatics (2012)
Keyphrases
- test set
- low power
- bipartite matching
- power consumption
- low cost
- high speed
- energy dissipation
- error rate
- training set
- maximum weight
- single chip
- minimum cost flow
- training data
- logic circuits
- mixed signal
- low power consumption
- image sensor
- vlsi architecture
- cmos technology
- sequential patterns
- vlsi circuits
- computer vision
- image processing
- np complete
- principal component analysis
- data sets