2 processor with 6-MB on-die L3 cache.
Simon TamRahul Dilip LimayeUtpal Nagarji DesaiPublished in: IEEE J. Solid State Circuits (2004)
Keyphrases
- processor core
- embedded processors
- memory subsystem
- memory hierarchy
- cache misses
- shared memory multiprocessors
- multithreading
- database workloads
- memory access
- shared memory multiprocessor
- single chip
- main memory
- high speed
- prefetching
- memory management
- multiprocessor systems
- query processing
- parallel processing
- operating system
- times faster
- hit rate
- ibm zenterprise
- multi core processors
- data access
- inter frame
- instruction set
- access patterns
- computer architecture
- shared memory
- computing power
- hard disk
- cache management
- read write
- parallel computing
- data structure
- database management systems
- motion estimation