A 130-nm triple-V/sub t/ 9-MB third-level on-die cache for the 1.7-GHz Itanium/spl reg/ 2 processor.
Jonathan ChangStefan RusuJonathan ShoemakerSimon TamMing HuangMizan HaqueSiufu ChiuKevin TruongMesbah KarimGloria LeongKiran DesaiRichard GoeSandhya KulkarniPublished in: IEEE J. Solid State Circuits (2005)