Testable path delay fault cover for sequential circuits.

Angela Krstic Kwang-Ting Cheng Srimat T. Chakradhar

Published in: EURO-DAC (1996)

Keyphrases

power dissipation
fault diagnosis
fault detection
fault models
high speed
shortest path
destination node
path length
neural network
circuit design
analog vlsi
quantum computing
analog circuits
digital circuits
expert systems
asynchronous circuits
fault model
optimal path
minimum cost