Jindrich Zejda

Publication Activity (10 Years)

Years Active: 1994-2007
Publications (10 Years): 0

Publications

Rohit Kapur, Jindrich Zejda, Thomas W. Williams
Fundamentals of timing information for test: How simple can we get? ITC (2007)
Jindrich Zejda, Li Ding
TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks. ISQED (2006)
Alex Gyure, Alireza Kasnavi, Sam C. Lo, Peivand F. Tehrani, William Shu, Mahmoud Shahram, Joddy W. Wang, Jindrich Zejda
Noise Library Characterization for Large Capacity Static Noise Analysis Tools. ISQED (2005)
Alireza Kasnavi, Joddy W. Wang, Mahmoud Shahram, Jindrich Zejda
Analytical modeling of crosstalk noise waveforms using Weibull function. ICCAD (2004)
Jindrich Zejda, Paul Frain
General framework for removal of clock network pessimism. ICCAD (2002)
Jindrich Zejda, Eduard Cerny, S. Shenoy, Nicholas C. Rumin
Bounding Switching Activity in CMOS Circuits Using Constraint Resolution. ED&TC (1996)
Jindrich Zejda, Eduard Cerny
Gate-level timing verification using waveform narrowing. EURO-DAC (1994)