Najmi T. Jarwala

Publication Activity (10 Years)

Years Active: 1988-1997
Publications (10 Years): 0

Publications

Najmi T. Jarwala
Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules. J. Electron. Test. 10 (1-2) (1997)
J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard
Hardware-Software Co-Design for Test: It's the Last Straw! VTS (1996)
Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau
Lessons Learned from Practical Applications of BIST/B-S Technology. Asian Test Symposium (1996)
Bernd Könemann, Ben Bennetts, Najmi T. Jarwala, Benoit Nadeau-Dostie
Built-In Self-Test: Assuring System Integrity. Computer 29 (11) (1996)
Wuudiann Ke, Duy Le, Najmi T. Jarwala
A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus. ITC (1995)
Najmi T. Jarwala
Designing "Dual-Personality" IEEE 1149.1-Compliant Multi-Chip Modules. ITC (1994)
Najmi T. Jarwala, Chi W. Yau
A structured approach to board-level BIST using the boundary-scan master. Microprocess. Microsystems 17 (5) (1993)
Najmi T. Jarwala, Paul Stiling, Enn Tammaru, Chi W. Yau
A Framework for Boundary-Scan Based System Test Diagnosis. ITC (1992)
Najmi T. Jarwala, Chi W. Yau
Achieving Board-Level BIST Using the Boundary-Scan Master. ITC (1991)
Chi W. Yau, Najmi T. Jarwala
The boundary-scan master: target applications and functional requirements. ITC (1990)
Najmi T. Jarwala, Chi W. Yau
A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects. ITC (1989)
Najmi T. Jarwala, Chi W. Yau
A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects. ITC (1989)
Najmi T. Jarwala, Dhiraj K. Pradhan
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's. IEEE Trans. Computers 37 (10) (1988)