Chi W. Yau

Publication Activity (10 Years)

Years Active: 1986-1996
Publications (10 Years): 0

Publications

Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau
Lessons Learned from Practical Applications of BIST/B-S Technology. Asian Test Symposium (1996)
Najmi T. Jarwala, Chi W. Yau
A structured approach to board-level BIST using the boundary-scan master. Microprocess. Microsystems 17 (5) (1993)
Najmi T. Jarwala, Paul Stiling, Enn Tammaru, Chi W. Yau
A Framework for Boundary-Scan Based System Test Diagnosis. ITC (1992)
Najmi T. Jarwala, Chi W. Yau
Achieving Board-Level BIST Using the Boundary-Scan Master. ITC (1991)
Chi W. Yau, Najmi T. Jarwala
The boundary-scan master: target applications and functional requirements. ITC (1990)
Najmi T. Jarwala, Chi W. Yau
A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects. ITC (1989)
Najmi T. Jarwala, Chi W. Yau
A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects. ITC (1989)
Anton T. Dahbura, M. Ümit Uyar, Chi W. Yau
An Optimal Test Sequence for the JTAG/IEEE P1149.1 Test Access Port Controller. ITC (1989)
Chi W. Yau, Song-Lin Chang, Bruce F. Jordan, Joe J. Schwermann, Joan A. Wellman
Trouble-Shooting: A Key to Process Improvement. ITC (1988)
Chi W. Yau
Concurrent Test Generation Using AI Techniques. ITC (1986)