Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing.
Chun-Yi LeeJames Chien-Mo LiPublished in: J. Low Power Electron. (2007)
Keyphrases
- low power
- cmos technology
- single chip
- vlsi architecture
- ultra low power
- high speed
- low cost
- low power consumption
- mixed signal
- power consumption
- vlsi implementation
- power dissipation
- signal processor
- logic circuits
- digital signal processing
- nm technology
- gate array
- vlsi circuits
- circuit design
- analog to digital converter
- high power
- power reduction
- cmos image sensor
- wireless transmission
- micron cmos
- efficient implementation
- low voltage
- multi channel
- parallel processing
- hardware and software
- real time
- built in self test
- design methodology
- low complexity
- energy saving