Chester Liu

Publication Activity (10 Years)

Years Active: 2010-2022
Publications (10 Years): 10

Top Topics

Action Classification

Fpga Technology

Top Venues

IEEE J. Solid State Circuits

Publications

Teyuh Chou, Wei Tang, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang
NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging. VLSI Technology and Circuits (2022)
Chester Liu, Jacob Botimer, Zhengya Zhang
A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer. CICC (2021)
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference. IEEE J. Solid State Circuits 56 (2) (2021)
Sung-Gun Cho, Wei Tang, Chester Liu, Zhengya Zhang
PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. VLSI Circuits (2021)
Thomas Chen, Ching-En Lee, Chester Liu, Zhengya Zhang
A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification. IEEE J. Solid State Circuits 54 (7) (2019)
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang
SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS. VLSI Circuits (2019)
Chester Liu, Sung-Gun Cho, Zhengya Zhang
718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS. IEEE J. Solid State Circuits 53 (10) (2018)
Chester Liu, Zhengya Zhang
Inference and Learning Hardware Architecture for Neuro- Inspired Sparse Coding Algoerithm. BioCAS (2018)
Chester Liu, Sung-Gun Cho, Zhengya Zhang
718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS. A-SSCC (2017)
Phil Knag, Chester Liu, Zhengya Zhang
141mW 898GOPS sparse neuromorphic processor in 40nm CMOS. VLSI Circuits (2016)
Chester Liu
Implementation of a highly scalable blokus duo solver on FPGA. FPT (2013)
Chester Liu, En-Hua Ma, Wen-En Wei, Chien-Mo James Li, I-Chun Cheng, Yung-Hui Yeh
Placement Optimization of Flexible TFT Digital Circuits. IEEE Des. Test Comput. 28 (6) (2011)
Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li
Static timing analysis for flexible TFT circuits. DAC (2010)