PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA.
Sung-Gun ChoWei TangChester LiuZhengya ZhangPublished in: VLSI Circuits (2021)
Keyphrases
- field programmable gate array
- hardware implementation
- embedded systems
- image processing algorithms
- parallel computing
- fpga implementation
- software implementation
- image processing
- hardware design
- hardware architecture
- digital signal processing
- matrix multiplication
- computing systems
- computer architecture
- fpga technology
- massively parallel
- signal processing
- fpga device
- low rank
- reconfigurable hardware
- high speed
- linear algebra
- efficient implementation
- singular value decomposition
- xilinx virtex