718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS.
Chester LiuSung-Gun ChoZhengya ZhangPublished in: A-SSCC (2017)
Keyphrases
- sparse coding
- high speed
- silicon on insulator
- ibm power processor
- dictionary learning
- cmos technology
- sparse representation
- natural images
- linear combination
- parallel processing
- image classification
- unsupervised learning
- metal oxide semiconductor
- image representation
- low power
- generative model
- image patches
- visual words
- bit rate
- face recognition
- deep belief networks
- feature space
- instruction set
- object category recognition
- power consumption
- pattern recognition
- sparse codes
- multiscale
- data sets
- semi supervised
- principal component analysis
- object recognition
- high dimensional