Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits.

Shiue-Tsung Shen Wei-Hsiao Liu En-Hua Ma James Chien-Mo Li I-Chun Cheng

Published in: Asian Test Symposium (2009)

Keyphrases

low voltage
cmos technology
low power
power line
power consumption
power dissipation
parallel processing
random access memory
high speed
design considerations
leakage current
mixed signal
power management
low cost
image sensor
thin film
wireless sensor networks
high resolution
real time