On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines.

Jiun-Lang Huang

Published in: J. Electron. Test. (2006)

Keyphrases

high speed
end to end delay
low cost
multiresolution
high levels
hough transform
packet loss
line drawings
straight line
power dissipation
coarse to fine
test cases
low power consumption
analog vlsi
image sequences
line segments
sufficient conditions
aggregation functions
functional verification
finer level