An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing.

Wei Chang Yu-Guang Chen Po-Yeh Huang Jin-Fu Li

Published in: DFT (2021)

Keyphrases

boolean logic
power consumption
random access memory
low power
design process
cmos technology
low cost
main memory
query processing
high speed
data transmission
design considerations
single chip
power dissipation