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A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines.
Shun-Hsun Yang
Yu-Jen Huang
Jin-Fu Li
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2012)
Keyphrases
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low power
content addressable memory
high speed
digital signal processing
real time
single chip
power consumption
low cost
vlsi circuits
image sensor
logic circuits
low power consumption
vlsi architecture
signal processing
gate array
processing elements
access control