Che-Wei Chou

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 6

Top Topics

Cyclic Scheduling

Route Selection

Hybrid Genetic Algorithm

Material Handling

Top Venues

IEEE Trans Autom. Sci. Eng.

Publications

Xiang-Li Lu, Hwai-Jung Hsu, Che-Wei Chou, H. T. Kung, Chen-Hsin Lee, Sheng-Mao Cheng
DeepMachining: Online Prediction of Machining Errors of Lathe Machines. CoRR (2024)
Hung-Kai Wang, Chen-Fu Chien, Che-Wei Chou
An empirical study of bio manufacturing for the scheduling of hepatitis in vitro diagnostic device with constrained process time window. Comput. Ind. Eng. 114 (2017)
Che-Wei Chou, Li-Hsing Yen
Autonomous Deployment of UAVs as Access Points to Serve Wireless Terminals. VTC Fall (2017)
Chen-Fu Chien, Che-Wei Chou, Hui-Chun Yu
A Novel Route Selection and Resource Allocation Approach to Improve the Efficiency of Manual Material Handling System in 200-mm Wafer Fabs for Industry 3.5. IEEE Trans Autom. Sci. Eng. 13 (4) (2016)
Che-Wei Chou, Jin-Fu Li, Yun-Chao Yu, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
Hierarchical Test Integration Methodology for 3-D ICs. IEEE Des. Test 32 (4) (2015)
Che-Wei Chou, Yong-Xiao Chen, Jin-Fu Li
Testing Inter-Word Coupling Faults of Wide I/O DRAMs. ATS (2015)
Che-Wei Chou, Chen-Fu Chien, Mitsuo Gen
A Multiobjective Hybrid Genetic Algorithm for TFT-LCD Module Assembly Scheduling. IEEE Trans Autom. Sci. Eng. 11 (3) (2014)
Chi-Chun Yang, Che-Wei Chou, Jin-Fu Li
A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs. Asian Test Symposium (2013)
Che-Wei Chou, Yu-Jen Huang, Jin-Fu Li
A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (4) (2013)
Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A built-in self-test scheme for 3D RAMs. ITC (2012)
Yu-Jen Huang, Jin-Fu Li, Che-Wei Chou
Post-bond test techniques for TSVs with crosstalk faults in 3D ICs. VLSI-DAT (2012)
Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A Test Integration Methodology for 3D Integrated Circuits. Asian Test Symposium (2010)
Yu-Jen Huang, Che-Wei Chou, Jin-Fu Li
A low-cost built-in self-test scheme for an array of memories. ETS (2010)
Chih-Sheng Hou, Jin-Fu Li, Che-Wei Chou
Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs. DELTA (2010)