​
Login / Signup
Pei-Wen Luo
Publication Activity (10 Years)
Years Active: 2008-2016
Publications (10 Years): 2
Top Topics
Integrated Circuit
Adaptive Filtering
Power Grid
Noise Reduction
Top Venues
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
ACM Trans. Design Autom. Electr. Syst.
ISPD
VLSIC
</>
Publications
</>
Tao Wang
,
Chun Zhang
,
Jinjun Xiong
,
Pei-Wen Luo
,
Liang-Chia Cheng
,
Yiyu Shi
On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
35 (10) (2016)
Hui Geng
,
Jianming Liu
,
Jinglan Liu
,
Pei-Wen Luo
,
Liang-Chia Cheng
,
Steven L. Grant
,
Yiyu Shi
Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling.
Integr.
55 (2016)
Hui Geng
,
Jianming Liu
,
Pei-Wen Luo
,
Liang-Chia Cheng
,
Steven L. Grant
,
Yiyu Shi
Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
34 (5) (2015)
Chien-Chih Huang
,
Chin-Long Wey
,
Jwu-E Chen
,
Pei-Wen Luo
Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs.
ACM Trans. Design Autom. Electr. Syst.
21 (1) (2015)
Pei-Wen Luo
,
Chi-Kang Chen
,
Yu-Hui Sung
,
Wei Wu
,
Hsiu-Chuan Shih
,
Chia-Hsin Lee
,
Kuo-Hua Lee
,
Ming-Wei Li
,
Mei-Chiang Lung
,
Chun-Nan Lu
,
Yung-Fa Chou
,
Po-Lin Shih
,
Chung-Hu Ke
,
Chun Shiah
,
Patrick Stolt
,
Shigeki Tomishima
,
Ding-Ming Kwai
,
Bor-Doou Rong
,
Nicky Lu
,
Shih-Lien Lu
,
Cheng-Wen Wu
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.
VLSIC
(2015)
Tao Wang
,
Chun Zhang
,
Jinjun Xiong
,
Pei-Wen Luo
,
Liang-Chia Cheng
,
Yiyu Shi
Variation aware optimal threshold voltage computation for on-chip noise sensors.
ICCAD
(2014)
Hsiu-Chuan Shih
,
Pei-Wen Luo
,
Jen-Chieh Yeh
,
Shu-Yen Lin
,
Ding-Ming Kwai
,
Shih-Lien Lu
,
Andre Schaefer
,
Cheng-Wen Wu
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
33 (9) (2014)
Chien-Chih Huang
,
Chin-Long Wey
,
Jwu-E Chen
,
Pei-Wen Luo
Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits.
ACM Trans. Design Autom. Electr. Syst.
19 (1) (2013)
Pei-Wen Luo
,
Chun Zhang
,
Yung-Tai Chang
,
Liang-Chia Cheng
,
Hung-Hsie Lee
,
Bih-Lan Sheu
,
Yu-Shih Su
,
Ding-Ming Kwai
,
Yiyu Shi
Benchmarking for research in power delivery networks of three-dimensional integrated circuits.
ISPD
(2013)
Tao Wang
,
Pei-Wen Luo
,
Yu-Shih Su
,
Liang-Chia Cheng
,
Ding-Ming Kwai
,
Yiyu Shi
Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction.
ASP-DAC
(2012)
Pei-Wen Luo
,
Tao Wang
,
Chin-Long Wey
,
Liang-Chia Cheng
,
Bih-Lan Sheu
,
Yiyu Shi
Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs).
ISVLSI
(2012)
Chien-Chih Huang
,
Jwu-E Chen
,
Pei-Wen Luo
,
Chin-Long Wey
Yield-award placement optimization for Switched-Capacitor analog integrated circuits.
SoCC
(2011)
Pei-Wen Luo
,
Jwu-E Chen
,
Chin-Long Wey
Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(1) (2011)
Jwu-E Chen
,
Pei-Wen Luo
,
Chin-Long Wey
Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
29 (2) (2010)
Jwu-E Chen
,
Pei-Wen Luo
,
Chin-Long Wey
Yield evaluation of analog placement with arbitrary capacitor ratio.
ISQED
(2009)
Pei-Wen Luo
,
Jwu-E Chen
,
Chin-Long Wey
,
Liang-Chia Cheng
,
Ji-Jan Chen
,
Wen Ching Wu
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
27 (11) (2008)