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A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.

Pei-Wen LuoChi-Kang ChenYu-Hui SungWei WuHsiu-Chuan ShihChia-Hsin LeeKuo-Hua LeeMing-Wei LiMei-Chiang LungChun-Nan LuYung-Fa ChouPo-Lin ShihChung-Hu KeChun ShiahPatrick StoltShigeki TomishimaDing-Ming KwaiBor-Doou RongNicky LuShih-Lien LuCheng-Wen Wu
Published in: VLSIC (2015)
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