Hsiu-Chuan Shih

Publication Activity (10 Years)

Years Active: 2011-2017
Publications (10 Years): 2

Top Topics

Ibm Power Processor

Top Venues

Publications

Zhi-Yong Liu, Hsiu-Chuan Shih, Bing-Yang Lin, Cheng-Wen Wu
Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache. IEEE Des. Test 34 (2) (2017)
Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. VLSIC (2015)
Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (9) (2014)
Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu
Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. ASP-DAC (2013)
Hsiu-Chuan Shih, Cheng-Wen Wu
An enhanced double-TSV scheme for defect tolerance in 3D-IC. DATE (2013)
Hsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu, Chih-He Lin, Shyh-Shyuan Sheu
Training-based forming process for RRAM yield improvement. VTS (2011)